[Bugfix][TIR] Fix cache_read update buffer region

[qsqqsqqsq-intellif]

Prior to this commit, cache_read primitive may not update the block reads buffer region properly when there is a nested buffer access.

@T.prim_func
def cache_read_nested_buffer_access(var_A: T.handle, var_B: T.handle, var_C: T.handle):
    for ax0, ax1 in T.grid(T.int64(1), T.int64(512)):
        with T.block("C"):
            v_ax0, v_ax1 = T.axis.remap("SS", [ax0, ax1])
            T.reads(A[B[v_ax0], v_ax1], B_global[v_ax0])
            T.writes(C[v_ax0, v_ax1])
            C[v_ax0, v_ax1] = A[B_global[v_ax0], v_ax1]

T.reads(A[B[v_ax0], v_ax1]) should be updated as T.reads(A[B_global[v_ax0], v_ax1])
cc @Hzfengsy