[LLVM][Codegen] Enable SVE/VLA for RISCV targets

[cbalint13]

This PR enables VLA (Vector-Length-Agnostic / Variable-Length-Array) predication for RISCV targets.

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New functionality:

• Enables existing SVE as generic VLA predication, extending the support done for aarch64 to riscv{32,64}

Changes:

• Vscale rage is now computed from arch specific vector_width (see disscuss), adapting to any vector ISA
• Split SVE related test cases between arch specific {riscv, aarch64} and llvm VLA generic (common) ones

UPDATE:

• Changed terms to generic VLA for common or non AArch64 parts (SVE remains ARM specific, RVV is riscv specific).

[cbalint13]

This is ready to review.

Cc: @lhutton1, @ekalda
Cc: @quic-sanirudh , @srkreddy1238
Cc: @Hzfengsy , @spectrometerHBH , @tqchen

Cc: @jerryzj , @JieGH

[tqchen]

Thanks @cbalint13 , do u mind rebase

[cbalint13]

Thanks @cbalint13 , do u mind rebase

I've re-based this to the latest head.