Skip to content

This repository contains the source codes for design of circuits written in VHDL using Xilinx (14.7), which were practiced as a part of my CA lab during my BTech 4th semester.

Notifications You must be signed in to change notification settings

arghyaxcodes/PCC-CS492-CA

Repository files navigation

Computer Architecture Lab (PCC-CS492)

VHDL Xilinx Ubuntu 22.10 GitHub last commit MIT License

This repository contains the source codes for design of various combinational and sequential circuits using logic gates and componenets written in VHDL using Xilinx (14.7), which were practiced as a part of my Computer Architecture Lab during my 4th semester.

Programs List

Group Files Link
Basic Gates AND, OR, NAND
Adders Half Adder, Full Adder, Full using Half Adder, 4 bit Adder, 8 bit Adder
Subtractors Half Subtractor, Full Subtractor, Full using Half Subtractor, 4 bit Subtractor, 8 bit Subtractor

Run Locally

Clone the project

  git clone https://github.com/uiuxarghya/PCC-CS492

Go to the project directory

  cd PCC-CS492

Feedback

Any suggestions and/or improvements are welcome. Please create a pull request or open an issue to submit your feedback.

Authors

License

MIT

About

This repository contains the source codes for design of circuits written in VHDL using Xilinx (14.7), which were practiced as a part of my CA lab during my BTech 4th semester.

Topics

Resources

Stars

Watchers

Forks

Languages