Feature: Hazard3 example SoC on Icebreaker support

[ALTracer]

Detailed description

• This is a minor new feature (basic new target board support).
• The existing problem is BMDA detecting the JTAG TAP of Hazard3/ice40 but it's unknown to it. So no debugging is possible even though riscv32 debug should be already supported.
• The PR solves it by registering 0xdeadbeef TAP ID in jtag_devs.c table, and registering 0xe77 manufacturer to hazard3_probe which simply adds 0x0+128 KiB SPRAM of ice40up5k. I also add the icebreaker FTDI interface A configuration to BMDA ftdi_bmp table so that no solderbridge mods are required, which was convenient to me.

I didn't touch rp2350.c because uniprocessor Hazard3 is unrelated to that (also no flash support and no bootrom) but creating an entire translation unit for this seemed excessive buildsystem-wise.
Tested on 1bitSquared Icebreaker-v1.0e (FT2232H, iCE40UP5k) flashed with https://github.com/Wren6991/Hazard3 modified gateware, and BMDA.
Because progbuf-based memory access is unsupported in BMD, and Abstract Access Memory is not implemented in Hazard3, you need to synthesize with HAVE_SBA=1 (then it doesn't fit 5280 LC so I had to FAST_BRANCHCMP=0 and it also may fail 12 MHz timings, but hit 10 MHz). Also I changed PCF to swap Interface B and Interface A, likewise you can use PMOD 1 or 2 for JTAG DTM and wire up a real BMP that's faster than BMDA+FTDI HS MPSSE (10 KiB/s load/verify).

Your checklist for this pull request

• I've read the Code of Conduct
• I've read the guidelines for contributing to this repository
• It builds for hardware native (see Building the firmware)
• It builds as BMDA (see Building the BMDA)
• I've tested it to the best of my ability
• My commit messages provide a useful short description of what the commits do

Closing issues