JIT: Optimize "x & cns == cns" pattern

[EgorBo]

Noticed in #100999:

void Foo(int x)
{
    if ((x & 0xC000000) == 0xC000000)
        Console.WriteLine();
}

Codegen on arm64:

            and     w0, w1, #0xC000000
            mov     w1, #0xC000000
            cmp     w0, w1
            bne     G_M37282_IG05

Expected codegen:

            mov     w1, #0xC000000
            bics    wzr, w8, w1
            bne     G_M37282_IG05

x64 is suboptimal for it as well, current codegen:

       and      edx, 0xC000000
       cmp      edx, 0xC000000
       jne      SHORT G_M37282_IG04

^ should be not + test.

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[quantumhu]

Hi, I'd like to attempt this issue if no one else is, thanks!

[quantumhu]

I gave this fix a try, it seems to work for ARM, generating the bics instruction without a cmp.

However, on x_arch, I can get the andn instruction to be generated when hw intrinsics are enabled, but I'm unable to get the not test structure.

I can't figure out how to transform the tree of CMP(AND(NOT(x), y)) to turn into a test. There are options for GT_TEST_EQ and GT_TEST_NE, neither of which are what I want. I just want a TEST(NOT(x), y) structure where y is not necessarily 0 (TEST_EQ and TEST_NE both assume the second operand is 0). When I change the node type to GT_TEST, there's assert errors

Any tips that people can share about getting past this?

[quantumhu]

Hi @EgorBo, sorry to ping you, I figured out how to do the optimization change but I'm not sure how to interpret the pipeline results as I see some of them timed out. I also see a couple that are formatting related, but I can't seem to access the artifacts as described in the logs.

Here's the pull request: #103868

Edit, to be more specific, I see some of these errors:

Assertion failed 'OperIs(GT_CNS_INT)' in 'System.Decimal:IsEvenInteger(System.Decimal):ubyte'

I tried to find this assert, wasn't sure which it was. I also tried to JitDisasm this, but couldn't get it to work.
In addition, I am looking for a flag to set (but not sure what exists) that will make the bics save the result to wzr instead of an actual register

Thank you very much!

[varelen]

Hey @jakobbotsch @EgorBo, sorry if pinging you is not desired.

Since the original pull request #103868 was closed, I would like to try this one out if it's okay. I have a working version for x64 based on the code provided by EgorBo in the original PR and will test ARM64 in the next days.

Interesing is, that on x64 the generated code is:

not      edi
and      edi, 0xC000000
jne      SHORT G_M000_IG04

and not with the test instruction. Can or should I force a test instruction?

GCC also generates the code above with -O2 as seen in godbolt (https://godbolt.org/z/1EjrGvvTs) and interestingly with -O1 it generates the test instruction.
clang on the other hand always emits the test instruction.