The JIT isn't optimizing `>>>` in the same way as `Vector128.ShiftRightLogical` on ARM

[MihaZupan]

Noticed in #85189, >>> isn't optimized down to AdvSimd.ShiftRightLogical on ARM.
Tanner pointed at

runtime/src/coreclr/jit/hwintrinsicarm64.cpp

Lines 1520 to 1555 in a1d45c5

	case NI_Vector64_ShiftLeft:
	case NI_Vector128_ShiftLeft:
	{
	assert(sig->numArgs == 2);
	op2 = impPopStack().val;
	op1 = impSIMDPopStack();
	retNode = gtNewSimdBinOpNode(GT_LSH, retType, op1, op2, simdBaseJitType, simdSize);
	break;
	}
	case NI_Vector64_ShiftRightArithmetic:
	case NI_Vector128_ShiftRightArithmetic:
	{
	assert(sig->numArgs == 2);
	genTreeOps op = varTypeIsUnsigned(simdBaseType) ? GT_RSZ : GT_RSH;
	op2 = impPopStack().val;
	op1 = impSIMDPopStack();
	retNode = gtNewSimdBinOpNode(op, retType, op1, op2, simdBaseJitType, simdSize);
	break;
	}
	case NI_Vector64_ShiftRightLogical:
	case NI_Vector128_ShiftRightLogical:
	{
	assert(sig->numArgs == 2);
	op2 = impPopStack().val;
	op1 = impSIMDPopStack();
	retNode = gtNewSimdBinOpNode(GT_RSZ, retType, op1, op2, simdBaseJitType, simdSize);
	break;
	}

as the relevant code.

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Issue Details

---

Noticed in #85189, >>> isn't optimized down to AdvSimd.ShiftRightLogical on ARM.
Tanner pointed at

runtime/src/coreclr/jit/hwintrinsicarm64.cpp

Lines 1520 to 1555 in a1d45c5

	case NI_Vector64_ShiftLeft:
	case NI_Vector128_ShiftLeft:
	{
	assert(sig->numArgs == 2);
	op2 = impPopStack().val;
	op1 = impSIMDPopStack();
	retNode = gtNewSimdBinOpNode(GT_LSH, retType, op1, op2, simdBaseJitType, simdSize);
	break;
	}
	case NI_Vector64_ShiftRightArithmetic:
	case NI_Vector128_ShiftRightArithmetic:
	{
	assert(sig->numArgs == 2);
	genTreeOps op = varTypeIsUnsigned(simdBaseType) ? GT_RSZ : GT_RSH;
	op2 = impPopStack().val;
	op1 = impSIMDPopStack();
	retNode = gtNewSimdBinOpNode(op, retType, op1, op2, simdBaseJitType, simdSize);
	break;
	}
	case NI_Vector64_ShiftRightLogical:
	case NI_Vector128_ShiftRightLogical:
	{
	assert(sig->numArgs == 2);
	op2 = impPopStack().val;
	op1 = impSIMDPopStack();
	retNode = gtNewSimdBinOpNode(GT_RSZ, retType, op1, op2, simdBaseJitType, simdSize);
	break;
	}

as the relevant code.

Author:	MihaZupan
Assignees:	-
Labels:	area-CodeGen-coreclr
Milestone:	-