[Wasm RyuJIT] Codegen for Const Vector Create and Basic Packed SIMD operations

src/coreclr/jit/codegen.h

@@ -796,6 +796,9 @@ class CodeGen final : public CodeGenInterface
 
 #if defined(TARGET_WASM)
     void genCodeForConstant(GenTree* treeNode);
+#if defined(FEATURE_SIMD)
+    void genCodeForVectorConstant(GenTree* treeNode);
+#endif
     void genCatchArg(GenTree* treeNode);
 #endif
 

src/coreclr/jit/codegenwasm.cpp

@@ -828,6 +828,14 @@ void CodeGen::genCodeForTreeNode(GenTree* treeNode)
         return;
     }
 
+#ifdef FEATURE_HW_INTRINSICS
+    if (treeNode->OperIsHWIntrinsic())
+    {
+        genHWIntrinsic(treeNode->AsHWIntrinsic());
+        return;
+    }
+#endif // FEATURE_HW_INTRINSICS
+
     switch (treeNode->OperGet())
     {
         case GT_ADD:
@@ -1004,6 +1012,12 @@ void CodeGen::genCodeForTreeNode(GenTree* treeNode)
             genCkfinite(treeNode);
             break;
 
+#if defined(FEATURE_SIMD)
+        case GT_CNS_VEC:
+            genCodeForVectorConstant(treeNode);
+            break;
+#endif // FEATURE_SIMD
+
         default:
 #ifdef DEBUG
             if (JitConfig.JitWasmNyiToR2RUnsupported())
@@ -1883,6 +1897,22 @@ void CodeGen::genCodeForConstant(GenTree* treeNode)
     WasmProduceReg(treeNode);
 }
 
+#ifdef FEATURE_SIMD
+void CodeGen::genCodeForVectorConstant(GenTree* treeNode)
+{
+    assert(treeNode->IsCnsVec());
+    GenTreeVecCon* vecCon = treeNode->AsVecCon();
+
+    uint8_t bytes[16] = {};
+    memcpy(bytes, &vecCon->gtSimdVal, genTypeSize(vecCon->TypeGet()));
+
+    // There is only one type variant for v128.const, v128.const <byte[16]>
+    // and the bytes are reinterpreted according to whichever operation consumes the value.
+    GetEmitter()->emitIns_V128Imm(INS_v128_const, bytes);
+    WasmProduceReg(treeNode);
+}
+#endif
+
 //------------------------------------------------------------------------
 // genCodeForShift: Generate code for a shift or rotate operator
 //
@@ -2553,10 +2583,6 @@ void CodeGen::genCodeForLclVar(GenTreeLclVar* tree)
     if (!varDsc->lvIsRegCandidate())
     {
         var_types type = varDsc->GetRegisterType(tree);
-        if (type == TYP_SIMD16)
-        {
-            NYI_WASM_SIMD("SIMD16 local load");
-        }
 
         GetEmitter()->emitIns_I(INS_local_get, EA_PTRSIZE, GetFramePointerRegIndex());
         GetEmitter()->emitIns_S(ins_Load(type), emitTypeSize(type), tree->GetLclNum(), 0);
@@ -2642,13 +2668,8 @@ void CodeGen::genCodeForIndir(GenTreeIndir* tree)
 {
     assert(tree->OperIs(GT_IND));
 
-    var_types type = tree->TypeGet();
-    if (type == TYP_SIMD16)
-    {
-        NYI_WASM_SIMD("SIMD16 indirect load");
-    }
-
-    instruction ins = ins_Load(type);
+    var_types   type = tree->TypeGet();
+    instruction ins  = ins_Load(type);
 
     genConsumeAddress(tree->Addr());
 

src/coreclr/jit/compiler.cpp

@@ -2024,6 +2024,13 @@ void Compiler::compSetProcessor()
     // Add virtual vector ISAs. These are both supported as part of the required baseline.
     instructionSetFlags.AddInstructionSet(InstructionSet_Vector64);
     instructionSetFlags.AddInstructionSet(InstructionSet_Vector128);
+#elif defined(TARGET_WASM)
+    // Ensure required baseline ISAs are supported in JIT code, even if not passed in by the VM.
+    instructionSetFlags.AddInstructionSet(InstructionSet_WasmBase);
+    instructionSetFlags.AddInstructionSet(InstructionSet_PackedSimd);
+
+    // Add virtual vector ISA. Vector128 is part of the required Wasm SIMD baseline.
+    instructionSetFlags.AddInstructionSet(InstructionSet_Vector128);
 #endif // TARGET_ARM64
 
     assert(instructionSetFlags.Equals(EnsureInstructionSetFlagsAreValid(instructionSetFlags)));

src/coreclr/jit/compiler.h

@@ -5152,6 +5152,11 @@ class Compiler
     GenTree* impImportLdvirtftn(GenTree* thisPtr, CORINFO_RESOLVED_TOKEN* pResolvedToken, CORINFO_CALL_INFO* pCallInfo);
 
 #if defined(FEATURE_HW_INTRINSICS)
+    GenTree* impSimdCreate(NamedIntrinsic    intrinsic,
+                           CORINFO_SIG_INFO* sig,
+                           var_types         simdBaseType,
+                           var_types         retType,
+                           unsigned          simdSize);
     GenTree* impSimdCreateScalarHalf(GenTree* op1);
     GenTree* impSimdToScalarHalf(GenTree* op1, CORINFO_CLASS_HANDLE halfClsHnd);
 #endif // FEATURE_HW_INTRINSICS

src/coreclr/jit/gentree.cpp

@@ -4777,6 +4777,13 @@ unsigned Compiler::gtSetMultiOpOrder(GenTreeMultiOp* multiOp)
         // We want the more complex tree to be evaluated first.
         if ((level < lvl2) && !multiOp->AsHWIntrinsic()->IsUserCall() && gtCanSwapOrder(op1, op2))
         {
+#if defined(TARGET_WASM)
+            // TODO-WASM-CQ: Wasm's stack-machine codegen requires operands to be evaluated in
+            // source order, so we cannot honor GTF_REVERSE_OPS here. For commutative HW
+            // intrinsics we could instead physically swap multiOp->Op(1)/Op(2) to retain the
+            // CQ benefit (mirroring the binary commutative path in gtSetEvalOrder). For now,
+            // just skip the swap to keep evaluation order intact.
+#else
             if (multiOp->IsReverseOp())
             {
                 multiOp->ClearReverseOp();
@@ -4787,6 +4794,7 @@ unsigned Compiler::gtSetMultiOpOrder(GenTreeMultiOp* multiOp)
             }
 
             std::swap(level, lvl2);
+#endif // TARGET_WASM
         }
 
         if (level < 1)

src/coreclr/jit/hwintrinsic.cpp

@@ -1048,9 +1048,8 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = {
     { NI_Illegal, NI_Illegal },                                 //      SveSm4_Arm64
 #elif defined(TARGET_WASM)
     { NI_Illegal, NI_Illegal },                                 //      WasmBase
-    { NI_Illegal, NI_Illegal },                                 //      PackedSimd
+    { FIRST_NI_PackedSimd, LAST_NI_PackedSimd },                // PackedSimd
     { FIRST_NI_Vector128, LAST_NI_Vector128 },                  // Vector128
-    // TODO-WASM: Add PackedSimd intrinsic ranges
 #else
 #error Unsupported platform
 #endif
@@ -1605,6 +1604,173 @@ GenTree* Compiler::getArgForHWIntrinsic(var_types argType, CORINFO_CLASS_HANDLE
     return arg;
 }
 
+//------------------------------------------------------------------------
+// impSimdCreate: Common importer logic for Vector{64,128,256,512}.Create intrinsics.
+//
+// Handles the shared pattern used across xarch, arm64, and wasm:
+//   * sig->numArgs == 1                    -> emit a broadcast/splat node
+//   * sig->numArgs == simdLength, all const-> fold into a single GenTreeVecCon
+//   * otherwise                            -> pack operands into a GT_HWINTRINSIC
+//                                             via IntrinsicNodeBuilder
+//
+// Arguments:
+//    intrinsic    -- the NI_Vector*_Create NamedIntrinsic being imported
+//    sig          -- the call signature (used for numArgs)
+//    simdBaseType -- the base element type of the SIMD vector
+//    retType      -- the SIMD return type
+//    simdSize     -- size in bytes of the SIMD vector
+//
+// Return Value:
+//    The imported GenTree* representing the Create call. Operands are popped
+//    off the importer stack as part of this call.
+//
+GenTree* Compiler::impSimdCreate(
+    NamedIntrinsic intrinsic, CORINFO_SIG_INFO* sig, var_types simdBaseType, var_types retType, unsigned simdSize)
+{
+    if (sig->numArgs == 1)
+    {
+        GenTree* op1 = impStackTop().val;
+
+#ifdef TARGET_WASM
+        if (!(op1->IsIntegralConst() || op1->IsCnsFltOrDbl()))
+        {
+            // Vector*.Create(T) with a non-constant operand is not yet supported on Wasm.
+            // Returning nullptr lets the importer fall back to the managed implementation.
+            return nullptr;
+        }
+#endif
+
+        op1 = impPopStack().val;
+        return gtNewSimdCreateBroadcastNode(retType, op1, simdBaseType, simdSize);
+    }
+
+    uint32_t simdLength = getSIMDVectorLength(simdSize, simdBaseType);
+    assert(sig->numArgs == simdLength);
+
+    bool isConstant = true;
+
+    if (varTypeIsFloating(simdBaseType))
+    {
+        for (uint32_t index = 0; index < sig->numArgs; index++)
+        {
+            if (!impStackTop(index).val->IsCnsFltOrDbl())
+            {
+                isConstant = false;
+                break;
+            }
+        }
+    }
+    else
+    {
+        assert(varTypeIsIntegral(simdBaseType));
+
+        for (uint32_t index = 0; index < sig->numArgs; index++)
+        {
+            if (!impStackTop(index).val->IsIntegralConst())
+            {
+                isConstant = false;
+                break;
+            }
+        }
+    }
+
+    if (isConstant)
+    {
+        GenTreeVecCon* vecCon = gtNewVconNode(retType);
+
+        switch (simdBaseType)
+        {
+            case TYP_BYTE:
+            case TYP_UBYTE:
+            {
+                for (uint32_t index = 0; index < sig->numArgs; index++)
+                {
+                    uint8_t cnsVal = static_cast<uint8_t>(impPopStack().val->AsIntConCommon()->IntegralValue());
+                    vecCon->gtSimdVal.u8[simdLength - 1 - index] = cnsVal;
+                }
+                break;
+            }
+
+            case TYP_SHORT:
+            case TYP_USHORT:
+            {
+                for (uint32_t index = 0; index < sig->numArgs; index++)
+                {
+                    uint16_t cnsVal = static_cast<uint16_t>(impPopStack().val->AsIntConCommon()->IntegralValue());
+                    vecCon->gtSimdVal.u16[simdLength - 1 - index] = cnsVal;
+                }
+                break;
+            }
+
+            case TYP_INT:
+            case TYP_UINT:
+            {
+                for (uint32_t index = 0; index < sig->numArgs; index++)
+                {
+                    uint32_t cnsVal = static_cast<uint32_t>(impPopStack().val->AsIntConCommon()->IntegralValue());
+                    vecCon->gtSimdVal.u32[simdLength - 1 - index] = cnsVal;
+                }
+                break;
+            }
+
+            case TYP_LONG:
+            case TYP_ULONG:
+            {
+                for (uint32_t index = 0; index < sig->numArgs; index++)
+                {
+                    uint64_t cnsVal = static_cast<uint64_t>(impPopStack().val->AsIntConCommon()->IntegralValue());
+                    vecCon->gtSimdVal.u64[simdLength - 1 - index] = cnsVal;
+                }
+                break;
+            }
+
+            case TYP_FLOAT:
+            {
+                for (uint32_t index = 0; index < sig->numArgs; index++)
+                {
+                    float cnsVal = static_cast<float>(impPopStack().val->AsDblCon()->DconValue());
+                    vecCon->gtSimdVal.f32[simdLength - 1 - index] = cnsVal;
+                }
+                break;
+            }
+
+            case TYP_DOUBLE:
+            {
+                for (uint32_t index = 0; index < sig->numArgs; index++)
+                {
+                    double cnsVal = static_cast<double>(impPopStack().val->AsDblCon()->DconValue());
+                    vecCon->gtSimdVal.f64[simdLength - 1 - index] = cnsVal;
+                }
+                break;
+            }
+
+            default:
+            {
+                unreached();
+            }
+        }
+
+        return vecCon;
+    }
+#ifdef TARGET_WASM
+    else
+    {
+        // non const Vector128.Create not yet implemented on Wasm
+        return nullptr;
+    }
+#endif
+
+    IntrinsicNodeBuilder nodeBuilder(getAllocator(CMK_ASTNode), sig->numArgs);
+
+    for (int i = sig->numArgs - 1; i >= 0; i--)
+    {
+        GenTree* arg = impPopStack().val;
+        nodeBuilder.AddOperand(i, arg);
+    }
+
+    return gtNewSimdHWIntrinsicNode(retType, std::move(nodeBuilder), intrinsic, simdBaseType, simdSize);
+}
+
 //------------------------------------------------------------------------
 // addRangeCheckIfNeeded: add a GT_BOUNDS_CHECK node for non-full-range imm-intrinsic
 //
@@ -2275,6 +2441,8 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic        intrinsic,
             if ((simdSize != 8) && (simdSize != 16) && (simdSize != SIZE_UNKNOWN))
 #elif defined(TARGET_XARCH)
             if ((simdSize != 16) && (simdSize != 32) && (simdSize != 64))
+#elif defined(TARGET_WASM)
+            if (simdSize != 16)
 #endif // TARGET_*
             {
                 assert(!"Unexpected SIMD size");