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[RyuJIT Wasm] SIMD Element-Wise Loads and Stores #130822

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Merged
adamperlin merged 13 commits into from
Jul 20, 2026
Merged

[RyuJIT Wasm] SIMD Element-Wise Loads and Stores #130822

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1050151
Add PackedSimd load/store mappings to table
adamperlin Jul 14, 2026
45f618e
Fix OperIsMemory{Load,Store} for PackedSimd operations
adamperlin Jul 15, 2026
7fd077a
Implement SIMD element-wise load/store codegen
adamperlin Jul 15, 2026
00c8430
Merge branch 'main' into adamperlin/wasm-simd-loads-stores
adamperlin Jul 15, 2026
8d07863
Enable null checks for PackedSimd loads/stores
adamperlin Jul 17, 2026
0df646a
Apply suggestions from code review
adamperlin Jul 17, 2026
6ddbd32
Add PackedSimdTests to exercise null check for loads/stores
adamperlin Jul 17, 2026
b9e3468
Merge branch 'main' into adamperlin/wasm-simd-loads-stores
adamperlin Jul 17, 2026
f1f45ce
jit-format
adamperlin Jul 17, 2026
7fd3953
Merge branch 'main' into adamperlin/wasm-simd-loads-stores
adamperlin Jul 17, 2026
e78535b
Fix segfault in release: move side effecting statement out of assert()
adamperlin Jul 18, 2026
bdbba8c
jit-format
adamperlin Jul 20, 2026
6709418
Merge branch 'main' into adamperlin/wasm-simd-loads-stores
adamperlin Jul 20, 2026
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10 changes: 2 additions & 8 deletions src/coreclr/jit/codegenwasm.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2862,14 +2862,8 @@ void CodeGen::genCodeForStoreInd(GenTreeStoreInd* tree)
}
else // A normal store, not a WriteBarrier store
{
var_types type = tree->TypeGet();
if (type == TYP_SIMD16)
{
// Storing a SIMD16 value emits v128.store, but the data operand is not
// materialized as a v128 (it comes through as an i32), producing an invalid
// module. Bail until SIMD16 store is properly supported.
NYI_WASM_SIMD("SIMD16 store indirect");
}
var_types type = tree->TypeGet();
instruction ins = ins_Store(type);

// TODO-WASM: Memory barriers

Expand Down
8 changes: 4 additions & 4 deletions src/coreclr/jit/gentree.cpp
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Expand Up @@ -30774,7 +30774,7 @@ bool GenTreeHWIntrinsic::OperIsMemoryLoad(GenTree** pAddr) const
{
GenTree* addr = nullptr;

#if defined(TARGET_XARCH) || defined(TARGET_ARM64)
#if defined(TARGET_XARCH) || defined(TARGET_ARM64) || defined(TARGET_WASM)
NamedIntrinsic intrinsicId = GetHWIntrinsicId();
HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsicId);

Expand Down Expand Up @@ -30964,7 +30964,7 @@ bool GenTreeHWIntrinsic::OperIsMemoryLoad(GenTree** pAddr) const
}
}
#endif // TARGET_XARCH
#endif // TARGET_XARCH || TARGET_ARM64
#endif // TARGET_XARCH || TARGET_ARM64 || TARGET_WASM

if (pAddr != nullptr)
{
Expand Down Expand Up @@ -31031,7 +31031,7 @@ bool GenTreeHWIntrinsic::OperIsMemoryStore(GenTree** pAddr) const
{
GenTree* addr = nullptr;

#if defined(TARGET_XARCH) || defined(TARGET_ARM64)
#if defined(TARGET_XARCH) || defined(TARGET_ARM64) || defined(TARGET_WASM)
NamedIntrinsic intrinsicId = GetHWIntrinsicId();
HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsicId);

Expand Down Expand Up @@ -31104,7 +31104,7 @@ bool GenTreeHWIntrinsic::OperIsMemoryStore(GenTree** pAddr) const
}
}
#endif // TARGET_XARCH
#endif // TARGET_XARCH || TARGET_ARM64
#endif // TARGET_XARCH || TARGET_ARM64 || TARGET_WASM

if (pAddr != nullptr)
{
Expand Down
13 changes: 10 additions & 3 deletions src/coreclr/jit/hwintrinsic.h
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Expand Up @@ -264,6 +264,8 @@ enum HWIntrinsicFlag : uint64_t
// The intrinsic supports some sort of containment analysis
HW_Flag_SupportsContainment = 0x400,
HW_Flag_ReturnsPerElementMask = 0x800,
// The intrinsic has a required immediate operand
HW_Flag_HasImmediateOperand = 0x1000,
#else
#error Unsupported platform
#endif
Expand Down Expand Up @@ -1003,10 +1005,10 @@ struct HWIntrinsicInfo

static bool HasImmediateOperand(NamedIntrinsic id)
{
#if defined(TARGET_ARM64)
#if defined(TARGET_ARM64) || defined(TARGET_WASM)
const HWIntrinsicFlag flags = lookupFlags(id);
return ((flags & HW_Flag_HasImmediateOperand) != 0);
#elif defined(TARGET_XARCH) || defined(TARGET_WASM)
#elif defined(TARGET_XARCH)
return lookupCategory(id) == HW_Category_IMM;
#else
return false;
Expand Down Expand Up @@ -1472,7 +1474,12 @@ struct HWIntrinsic final

inline bool needsJumpTableFallback() const
{
return !m_node->GetImmOp()->IsCnsIntOrI();
if (HWIntrinsicInfo::HasImmediateOperand(id))
{
return !m_node->GetImmOp()->IsCnsIntOrI();
}

return false;
}

uint8_t GetImmediateLaneOperand() const
Expand Down
39 changes: 38 additions & 1 deletion src/coreclr/jit/hwintrinsiccodegenwasm.cpp
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Expand Up @@ -70,6 +70,32 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
}
break;
}
case HW_Category_MemoryStore:
case HW_Category_MemoryLoad:
{
emitAttr elemSize = emitActualTypeSize(node->GetSimdBaseType());
GenTree* addr = nullptr;
bool isMem = node->OperIsMemoryLoad(&addr) || node->OperIsMemoryStore(&addr);
assert(isMem && addr != nullptr);

regNumber addrReg = GetMultiUseOperandReg(addr);
genEmitNullCheck(addrReg);

if (info.needsJumpTableFallback())
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{
genHWIntrinsicJumpTableFallback(node, info);
}
else if (HWIntrinsicInfo::HasImmediateOperand(info.id))
{
GetEmitter()->emitIns_MemargLane(ins, elemSize, 0, info.GetImmediateLaneOperand());
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}
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else
{
GetEmitter()->emitIns_I(ins, elemSize, 0);
}

break;
}
default:
{
NYI_WASM_SIMD("CodeGen::genHWIntrinsic: Unsupported category for table-driven intrinsic");
Expand Down Expand Up @@ -142,7 +168,11 @@ void CodeGen::genHWIntrinsicJumpTableFallback(GenTreeHWIntrinsic* node, HWIntrin
int simdSize = node->GetSimdSize();
instruction const ins = HWIntrinsicInfo::lookupIns(info.id, info.baseType, m_compiler);
int immUpperBound = HWIntrinsicInfo::lookupImmUpperBound(info.id, simdSize, info.baseType);
WasmValueType resultType = ActualTypeToWasmValueType(genActualType(node->TypeGet()));
WasmValueType resultType = WasmValueType::Invalid;
if (!node->TypeIs(TYP_VOID))
{
resultType = ActualTypeToWasmValueType(genActualType(node->TypeGet()));
}

GenTree* immOp = node->GetImmOp();
regNumber immReg = GetMultiUseOperandReg(immOp);
Expand Down Expand Up @@ -208,6 +238,13 @@ void CodeGen::genHWIntrinsicJumpTableFallback(GenTreeHWIntrinsic* node, HWIntrin
GetEmitter()->emitIns_Lane(ins, static_cast<uint8_t>(i));
break;
}
case HW_Category_MemoryLoad:
case HW_Category_MemoryStore:
{
emitAttr elemSize = emitActualTypeSize(node->GetSimdBaseType());
GetEmitter()->emitIns_MemargLane(ins, elemSize, 0, static_cast<uint8_t>(i));
break;
}
default:
{
NYI_WASM_SIMD(
Expand Down
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