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Adding EVEX encoding logic for RR/AM pathways #77419

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Merged
BruceForstall merged 4 commits into from
Nov 5, 2022
Merged

Adding EVEX encoding logic for RR/AM pathways #77419

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b172f73
Cleaning up TODO-XARCH-CLEANUP on EA_8BYTE size.
DeepakRajendrakumaran Oct 26, 2022
d6e5fd2
Adding EVEX encoding pathways for emitOutputRR().
DeepakRajendrakumaran Oct 26, 2022
2570374
Adding EVEX encoding support for AM paths.
DeepakRajendrakumaran Oct 27, 2022
0a1d2b9
Moving 'JitStressEvexEncoding' under Debug flag and other review clea…
DeepakRajendrakumaran Oct 27, 2022
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4 changes: 4 additions & 0 deletions src/coreclr/jit/codegen.h
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Expand Up @@ -1700,7 +1700,11 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

instruction ins_Copy(var_types dstType);
instruction ins_Copy(regNumber srcReg, var_types dstType);
#if defined(TARGET_XARCH)
instruction ins_FloatConv(var_types to, var_types from, emitAttr attr);
#elif defined(TARGET_ARM)
instruction ins_FloatConv(var_types to, var_types from);
#endif
instruction ins_MathOp(genTreeOps oper, var_types type);

void instGen_Return(unsigned stkArgSize);
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16 changes: 5 additions & 11 deletions src/coreclr/jit/codegenxarch.cpp
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Expand Up @@ -6911,7 +6911,7 @@ void CodeGen::genFloatToFloatCast(GenTree* treeNode)
}
else
{
instruction ins = ins_FloatConv(dstType, srcType);
instruction ins = ins_FloatConv(dstType, srcType, emitTypeSize(dstType));
GetEmitter()->emitInsBinary(ins, emitTypeSize(dstType), treeNode, op1);
}

Expand Down Expand Up @@ -7005,7 +7005,7 @@ void CodeGen::genIntToFloatCast(GenTree* treeNode)

// Note that here we need to specify srcType that will determine
// the size of source reg/mem operand and rex.w prefix.
instruction ins = ins_FloatConv(dstType, TYP_INT);
instruction ins = ins_FloatConv(dstType, TYP_INT, emitTypeSize(srcType));
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@BruceForstall BruceForstall Oct 29, 2022

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The other cases use emitTypeSize(dstType) but this uses srcType?

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@DeepakRajendrakumaran DeepakRajendrakumaran Nov 1, 2022 •
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Ah.. should be srcType . We are trying to differentiate between VCVTSI2SS xmm1, xmm2, m32 and VCVTSI2SS xmm1, xmm2, m64

GetEmitter()->emitInsBinary(ins, emitTypeSize(srcType), treeNode, op1);

// Handle the case of srcType = TYP_ULONG. SSE2 conversion instruction
Expand Down Expand Up @@ -7110,7 +7110,7 @@ void CodeGen::genFloatToIntCast(GenTree* treeNode)
// Note that we need to specify dstType here so that it will determine
// the size of destination integer register and also the rex.w prefix.
genConsumeOperands(treeNode->AsOp());
instruction ins = ins_FloatConv(TYP_INT, srcType);
instruction ins = ins_FloatConv(TYP_INT, srcType, emitTypeSize(srcType));
GetEmitter()->emitInsBinary(ins, emitTypeSize(dstType), treeNode, op1);
genProduceReg(treeNode);
}
Expand Down Expand Up @@ -10713,10 +10713,7 @@ void CodeGen::genPreserveCalleeSavedFltRegs(unsigned lclFrameSize)
if ((regBit & regMask) != 0)
{
// ABI requires us to preserve lower 128-bits of YMM register.
GetEmitter()->emitIns_AR_R(copyIns,
EA_8BYTE, // TODO-XArch-Cleanup: size specified here doesn't matter but should be
// EA_16BYTE
reg, REG_SPBASE, offset);
GetEmitter()->emitIns_AR_R(copyIns, EA_16BYTE, reg, REG_SPBASE, offset);
compiler->unwindSaveReg(reg, offset);
regMask &= ~regBit;
offset -= XMM_REGSIZE_BYTES;
Expand Down Expand Up @@ -10780,10 +10777,7 @@ void CodeGen::genRestoreCalleeSavedFltRegs(unsigned lclFrameSize)
if ((regBit & regMask) != 0)
{
// ABI requires us to restore lower 128-bits of YMM register.
GetEmitter()->emitIns_R_AR(copyIns,
EA_8BYTE, // TODO-XArch-Cleanup: size specified here doesn't matter but should be
// EA_16BYTE
reg, regBase, offset);
GetEmitter()->emitIns_R_AR(copyIns, EA_16BYTE, reg, regBase, offset);
regMask &= ~regBit;
offset -= XMM_REGSIZE_BYTES;
}
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18 changes: 11 additions & 7 deletions src/coreclr/jit/compiler.h
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Expand Up @@ -8993,7 +8993,8 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// canUseEvexEncoding - Answer the question: Is Evex encoding supported on this target.
//
// Returns:
// TRUE if Evex encoding is supported, FALSE if not.
// `true` if Evex encoding is supported, `false` if not.
//
bool canUseEvexEncoding() const
{
#ifdef TARGET_XARCH
Expand All @@ -9007,18 +9008,21 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// DoJitStressEvexEncoding- Answer the question: Do we force EVEX encoding.
//
// Returns:
// TRUE if user requests EVEX encoding and it's safe, FALSE if not.
// `true` if user requests EVEX encoding and it's safe, `false` if not.
//
bool DoJitStressEvexEncoding() const
{
#ifdef TARGET_XARCH
// Using JitStressEVEXEncoding flag will force instructions which would
// otherwise use VEX encoding but can be EVEX encoded to use EVEX encoding
// This requires AVX512VL support.
if (JitConfig.JitStressEVEXEncoding() && compOpportunisticallyDependsOn(InstructionSet_AVX512F_VL))
// Using JitStressEvexEncoding flag will force instructions which would
// otherwise use VEX encoding but can be EVEX encoded to use EVEX encoding
// This requires AVX512VL support.
#ifdef DEBUG
if (JitConfig.JitStressEvexEncoding() && compOpportunisticallyDependsOn(InstructionSet_AVX512F_VL))
{
return true;
}
#endif
#endif // DEBUG
#endif // TARGET_XARCH
return false;
}

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