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Merged
jkotas merged 2 commits into from
Nov 21, 2023
Merged

Add SVE InstructionSet for Arm64 #95021

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2dcb14a
Add SVE instruction set for Arm64
a74nh Nov 7, 2023
0b01169
Remove hwintrinsiclistarm64sve.h
a74nh Nov 21, 2023
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1 change: 1 addition & 0 deletions src/coreclr/inc/clrconfigvalues.h
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Expand Up @@ -798,6 +798,7 @@ RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sha1, W("EnableArm64Sh
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sha256, W("EnableArm64Sha256"), 1, "Allows Arm64 Sha256+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Rcpc, W("EnableArm64Rcpc"), 1, "Allows Arm64 Rcpc+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Rcpc2, W("EnableArm64Rcpc2"), 1, "Allows Arm64 Rcpc2+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableArm64Sve, W("EnableArm64Sve"), 1, "Allows Arm64 SVE hardware intrinsics to be disabled")
#endif

///
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31 changes: 23 additions & 8 deletions src/coreclr/inc/corinfoinstructionset.h
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Expand Up @@ -31,14 +31,16 @@ enum CORINFO_InstructionSet
InstructionSet_Rcpc=13,
InstructionSet_VectorT128=14,
InstructionSet_Rcpc2=15,
InstructionSet_ArmBase_Arm64=16,
InstructionSet_AdvSimd_Arm64=17,
InstructionSet_Aes_Arm64=18,
InstructionSet_Crc32_Arm64=19,
InstructionSet_Dp_Arm64=20,
InstructionSet_Rdm_Arm64=21,
InstructionSet_Sha1_Arm64=22,
InstructionSet_Sha256_Arm64=23,
InstructionSet_Sve=16,
InstructionSet_ArmBase_Arm64=17,
InstructionSet_AdvSimd_Arm64=18,
InstructionSet_Aes_Arm64=19,
InstructionSet_Crc32_Arm64=20,
InstructionSet_Dp_Arm64=21,
InstructionSet_Rdm_Arm64=22,
InstructionSet_Sha1_Arm64=23,
InstructionSet_Sha256_Arm64=24,
InstructionSet_Sve_Arm64=25,
#endif // TARGET_ARM64
#ifdef TARGET_AMD64
InstructionSet_X86Base=1,
Expand Down Expand Up @@ -282,6 +284,8 @@ struct CORINFO_InstructionSetFlags
AddInstructionSet(InstructionSet_Sha1_Arm64);
if (HasInstructionSet(InstructionSet_Sha256))
AddInstructionSet(InstructionSet_Sha256_Arm64);
if (HasInstructionSet(InstructionSet_Sve))
AddInstructionSet(InstructionSet_Sve_Arm64);
#endif // TARGET_ARM64
#ifdef TARGET_AMD64
if (HasInstructionSet(InstructionSet_X86Base))
Expand Down Expand Up @@ -394,6 +398,10 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
resultflags.RemoveInstructionSet(InstructionSet_Sha256);
if (resultflags.HasInstructionSet(InstructionSet_Sha256_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Sha256))
resultflags.RemoveInstructionSet(InstructionSet_Sha256_Arm64);
if (resultflags.HasInstructionSet(InstructionSet_Sve) && !resultflags.HasInstructionSet(InstructionSet_Sve_Arm64))
resultflags.RemoveInstructionSet(InstructionSet_Sve);
if (resultflags.HasInstructionSet(InstructionSet_Sve_Arm64) && !resultflags.HasInstructionSet(InstructionSet_Sve))
resultflags.RemoveInstructionSet(InstructionSet_Sve_Arm64);
if (resultflags.HasInstructionSet(InstructionSet_AdvSimd) && !resultflags.HasInstructionSet(InstructionSet_ArmBase))
resultflags.RemoveInstructionSet(InstructionSet_AdvSimd);
if (resultflags.HasInstructionSet(InstructionSet_Aes) && !resultflags.HasInstructionSet(InstructionSet_ArmBase))
Expand All @@ -414,6 +422,8 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
resultflags.RemoveInstructionSet(InstructionSet_Vector128);
if (resultflags.HasInstructionSet(InstructionSet_VectorT128) && !resultflags.HasInstructionSet(InstructionSet_AdvSimd))
resultflags.RemoveInstructionSet(InstructionSet_VectorT128);
if (resultflags.HasInstructionSet(InstructionSet_Sve) && !resultflags.HasInstructionSet(InstructionSet_AdvSimd))
resultflags.RemoveInstructionSet(InstructionSet_Sve);
#endif // TARGET_ARM64
#ifdef TARGET_AMD64
if (resultflags.HasInstructionSet(InstructionSet_X86Base) && !resultflags.HasInstructionSet(InstructionSet_X86Base_X64))
Expand Down Expand Up @@ -764,6 +774,10 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
return "VectorT128";
case InstructionSet_Rcpc2 :
return "Rcpc2";
case InstructionSet_Sve :
return "Sve";
case InstructionSet_Sve_Arm64 :
return "Sve_Arm64";
#endif // TARGET_ARM64
#ifdef TARGET_AMD64
case InstructionSet_X86Base :
Expand Down Expand Up @@ -998,6 +1012,7 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst
case READYTORUN_INSTRUCTION_Rcpc: return InstructionSet_Rcpc;
case READYTORUN_INSTRUCTION_VectorT128: return InstructionSet_VectorT128;
case READYTORUN_INSTRUCTION_Rcpc2: return InstructionSet_Rcpc2;
case READYTORUN_INSTRUCTION_Sve: return InstructionSet_Sve;
#endif // TARGET_ARM64
#ifdef TARGET_AMD64
case READYTORUN_INSTRUCTION_X86Base: return InstructionSet_X86Base;
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12 changes: 6 additions & 6 deletions src/coreclr/inc/jiteeversionguid.h
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Expand Up @@ -43,13 +43,13 @@ typedef const GUID *LPCGUID;
#define GUID_DEFINED
#endif // !GUID_DEFINED

constexpr GUID JITEEVersionIdentifier = { /* a2974440-e8ee-4d95-9e6e-799a330be1a0 */
0xa2974440,
0xe8ee,
0x4d95,
{0x9e, 0x6e, 0x79, 0x9a, 0x33, 0x0b, 0xe1, 0xa0}
constexpr GUID JITEEVersionIdentifier = { /* e15e62ce-d9c6-418a-a5a7-26ad17fcf4bf */
0xe15e62ce,
0xd9c6,
0x418a,
{0xa5, 0xa7, 0x26, 0xad, 0x17, 0xfc, 0xf4, 0xbf}
};

//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// END JITEEVersionIdentifier
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1 change: 1 addition & 0 deletions src/coreclr/inc/readytoruninstructionset.h
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Expand Up @@ -51,6 +51,7 @@ enum ReadyToRunInstructionSet
READYTORUN_INSTRUCTION_VectorT256=40,
READYTORUN_INSTRUCTION_VectorT512=41,
READYTORUN_INSTRUCTION_Rcpc2=42,
READYTORUN_INSTRUCTION_Sve=43,

};

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5 changes: 5 additions & 0 deletions src/coreclr/jit/compiler.cpp
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Expand Up @@ -6014,6 +6014,11 @@ int Compiler::compCompile(CORINFO_MODULE_HANDLE classPtr,
{
instructionSetFlags.AddInstructionSet(InstructionSet_Dczva);
}

if (JitConfig.EnableArm64Sve() != 0)
{
instructionSetFlags.AddInstructionSet(InstructionSet_Sve);
}
#elif defined(TARGET_XARCH)
if (JitConfig.EnableHWIntrinsic() != 0)
{
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8 changes: 8 additions & 0 deletions src/coreclr/jit/hwintrinsicarm64.cpp
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Expand Up @@ -34,6 +34,8 @@ static CORINFO_InstructionSet Arm64VersionOfIsa(CORINFO_InstructionSet isa)
return InstructionSet_Sha256_Arm64;
case InstructionSet_Rdm:
return InstructionSet_Rdm_Arm64;
case InstructionSet_Sve:
return InstructionSet_Sve_Arm64;
default:
return InstructionSet_NONE;
}
Expand Down Expand Up @@ -97,6 +99,10 @@ static CORINFO_InstructionSet lookupInstructionSet(const char* className)
{
return InstructionSet_Sha256;
}
if (strcmp(className, "Sve") == 0)
{
return InstructionSet_Sve;
}
}
else if (className[0] == 'V')
{
Expand Down Expand Up @@ -166,6 +172,8 @@ bool HWIntrinsicInfo::isFullyImplementedIsa(CORINFO_InstructionSet isa)
case InstructionSet_Sha1_Arm64:
case InstructionSet_Sha256:
case InstructionSet_Sha256_Arm64:
case InstructionSet_Sve:
case InstructionSet_Sve_Arm64:
case InstructionSet_Vector64:
case InstructionSet_Vector128:
return true;
Expand Down
1 change: 1 addition & 0 deletions src/coreclr/jit/jitconfigvalues.h
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Expand Up @@ -351,6 +351,7 @@ CONFIG_INTEGER(EnableArm64Dp, W("EnableArm64Dp"), 1) /
CONFIG_INTEGER(EnableArm64Rdm, W("EnableArm64Rdm"), 1) // Allows Arm64 Rdm+ hardware intrinsics to be disabled
CONFIG_INTEGER(EnableArm64Sha1, W("EnableArm64Sha1"), 1) // Allows Arm64 Sha1+ hardware intrinsics to be disabled
CONFIG_INTEGER(EnableArm64Sha256, W("EnableArm64Sha256"), 1) // Allows Arm64 Sha256+ hardware intrinsics to be disabled
CONFIG_INTEGER(EnableArm64Sve, W("EnableArm64Sve"), 1) // Allows Arm64 Sve+ hardware intrinsics to be disabled
#endif

// clang-format on
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5 changes: 5 additions & 0 deletions src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs
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Expand Up @@ -221,6 +221,7 @@ private static class Arm64IntrinsicConstants
public const int Rcpc = 0x0100;
public const int VectorT128 = 0x0200;
public const int Rcpc2 = 0x0400;
public const int Sve = 0x0800;

public static void AddToBuilder(InstructionSetSupportBuilder builder, int flags)
{
Expand All @@ -244,6 +245,8 @@ public static void AddToBuilder(InstructionSetSupportBuilder builder, int flags)
builder.AddSupportedInstructionSet("rcpc");
if ((flags & Rcpc2) != 0)
builder.AddSupportedInstructionSet("rcpc2");
if ((flags & Sve) != 0)
builder.AddSupportedInstructionSet("sve");
}

public static int FromInstructionSet(InstructionSet instructionSet)
Expand Down Expand Up @@ -273,6 +276,8 @@ public static int FromInstructionSet(InstructionSet instructionSet)
InstructionSet.ARM64_Atomics => Atomics,
InstructionSet.ARM64_Rcpc => Rcpc,
InstructionSet.ARM64_Rcpc2 => Rcpc2,
InstructionSet.ARM64_Sve => Sve,
InstructionSet.ARM64_Sve_Arm64 => Sve,

// Vector<T> Sizes
InstructionSet.ARM64_VectorT128 => VectorT128,
Expand Down
1 change: 1 addition & 0 deletions src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs
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Expand Up @@ -54,6 +54,7 @@ public enum ReadyToRunInstructionSet
VectorT256=40,
VectorT512=41,
Rcpc2=42,
Sve=43,

}
}
2 changes: 2 additions & 0 deletions src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs
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Expand Up @@ -46,6 +46,8 @@ public static class ReadyToRunInstructionSetHelper
case InstructionSet.ARM64_Rcpc: return ReadyToRunInstructionSet.Rcpc;
case InstructionSet.ARM64_VectorT128: return ReadyToRunInstructionSet.VectorT128;
case InstructionSet.ARM64_Rcpc2: return ReadyToRunInstructionSet.Rcpc2;
case InstructionSet.ARM64_Sve: return ReadyToRunInstructionSet.Sve;
case InstructionSet.ARM64_Sve_Arm64: return ReadyToRunInstructionSet.Sve;

default: throw new Exception("Unknown instruction set");
}
Expand Down
40 changes: 32 additions & 8 deletions src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs
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Expand Up @@ -31,6 +31,7 @@ public enum InstructionSet
ARM64_Rcpc = InstructionSet_ARM64.Rcpc,
ARM64_VectorT128 = InstructionSet_ARM64.VectorT128,
ARM64_Rcpc2 = InstructionSet_ARM64.Rcpc2,
ARM64_Sve = InstructionSet_ARM64.Sve,
ARM64_ArmBase_Arm64 = InstructionSet_ARM64.ArmBase_Arm64,
ARM64_AdvSimd_Arm64 = InstructionSet_ARM64.AdvSimd_Arm64,
ARM64_Aes_Arm64 = InstructionSet_ARM64.Aes_Arm64,
Expand All @@ -39,6 +40,7 @@ public enum InstructionSet
ARM64_Rdm_Arm64 = InstructionSet_ARM64.Rdm_Arm64,
ARM64_Sha1_Arm64 = InstructionSet_ARM64.Sha1_Arm64,
ARM64_Sha256_Arm64 = InstructionSet_ARM64.Sha256_Arm64,
ARM64_Sve_Arm64 = InstructionSet_ARM64.Sve_Arm64,
X64_X86Base = InstructionSet_X64.X86Base,
X64_SSE = InstructionSet_X64.SSE,
X64_SSE2 = InstructionSet_X64.SSE2,
Expand Down Expand Up @@ -187,14 +189,16 @@ public enum InstructionSet_ARM64
Rcpc = 13,
VectorT128 = 14,
Rcpc2 = 15,
ArmBase_Arm64 = 16,
AdvSimd_Arm64 = 17,
Aes_Arm64 = 18,
Crc32_Arm64 = 19,
Dp_Arm64 = 20,
Rdm_Arm64 = 21,
Sha1_Arm64 = 22,
Sha256_Arm64 = 23,
Sve = 16,
ArmBase_Arm64 = 17,
AdvSimd_Arm64 = 18,
Aes_Arm64 = 19,
Crc32_Arm64 = 20,
Dp_Arm64 = 21,
Rdm_Arm64 = 22,
Sha1_Arm64 = 23,
Sha256_Arm64 = 24,
Sve_Arm64 = 25,
}

public enum InstructionSet_X64
Expand Down Expand Up @@ -525,6 +529,10 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target
resultflags.AddInstructionSet(InstructionSet.ARM64_Sha256_Arm64);
if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sha256_Arm64))
resultflags.AddInstructionSet(InstructionSet.ARM64_Sha256);
if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve))
resultflags.AddInstructionSet(InstructionSet.ARM64_Sve_Arm64);
if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve_Arm64))
resultflags.AddInstructionSet(InstructionSet.ARM64_Sve);
if (resultflags.HasInstructionSet(InstructionSet.ARM64_AdvSimd))
resultflags.AddInstructionSet(InstructionSet.ARM64_ArmBase);
if (resultflags.HasInstructionSet(InstructionSet.ARM64_Aes))
Expand All @@ -545,6 +553,8 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target
resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd);
if (resultflags.HasInstructionSet(InstructionSet.ARM64_VectorT128))
resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd);
if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve))
resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd);
break;

case TargetArchitecture.X64:
Expand Down Expand Up @@ -874,6 +884,8 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe
resultflags.AddInstructionSet(InstructionSet.ARM64_Sha1);
if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sha256_Arm64))
resultflags.AddInstructionSet(InstructionSet.ARM64_Sha256);
if (resultflags.HasInstructionSet(InstructionSet.ARM64_Sve_Arm64))
resultflags.AddInstructionSet(InstructionSet.ARM64_Sve);
if (resultflags.HasInstructionSet(InstructionSet.ARM64_ArmBase))
resultflags.AddInstructionSet(InstructionSet.ARM64_AdvSimd);
if (resultflags.HasInstructionSet(InstructionSet.ARM64_ArmBase))
Expand All @@ -894,6 +906,8 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe
resultflags.AddInstructionSet(InstructionSet.ARM64_Vector128);
if (resultflags.HasInstructionSet(InstructionSet.ARM64_AdvSimd))
resultflags.AddInstructionSet(InstructionSet.ARM64_VectorT128);
if (resultflags.HasInstructionSet(InstructionSet.ARM64_AdvSimd))
resultflags.AddInstructionSet(InstructionSet.ARM64_Sve);
break;

case TargetArchitecture.X64:
Expand Down Expand Up @@ -1198,6 +1212,7 @@ public static IEnumerable<InstructionSetInfo> ArchitectureToValidInstructionSets
yield return new InstructionSetInfo("rcpc", "", InstructionSet.ARM64_Rcpc, true);
yield return new InstructionSetInfo("vectort128", "VectorT128", InstructionSet.ARM64_VectorT128, true);
yield return new InstructionSetInfo("rcpc2", "", InstructionSet.ARM64_Rcpc2, true);
yield return new InstructionSetInfo("sve", "Sve", InstructionSet.ARM64_Sve, true);
break;

case TargetArchitecture.X64:
Expand Down Expand Up @@ -1300,6 +1315,8 @@ public void Set64BitInstructionSetVariants(TargetArchitecture architecture)
AddInstructionSet(InstructionSet.ARM64_Sha1_Arm64);
if (HasInstructionSet(InstructionSet.ARM64_Sha256))
AddInstructionSet(InstructionSet.ARM64_Sha256_Arm64);
if (HasInstructionSet(InstructionSet.ARM64_Sve))
AddInstructionSet(InstructionSet.ARM64_Sve_Arm64);
break;

case TargetArchitecture.X64:
Expand Down Expand Up @@ -1382,6 +1399,7 @@ public void Set64BitInstructionSetVariantsUnconditionally(TargetArchitecture arc
AddInstructionSet(InstructionSet.ARM64_Rdm_Arm64);
AddInstructionSet(InstructionSet.ARM64_Sha1_Arm64);
AddInstructionSet(InstructionSet.ARM64_Sha256_Arm64);
AddInstructionSet(InstructionSet.ARM64_Sve_Arm64);
break;

case TargetArchitecture.X64:
Expand Down Expand Up @@ -1551,6 +1569,12 @@ public static InstructionSet LookupPlatformIntrinsicInstructionSet(TargetArchite
case "VectorT128":
{ return InstructionSet.ARM64_VectorT128; }

case "Sve":
if (nestedTypeName == "Arm64")
{ return InstructionSet.ARM64_Sve_Arm64; }
else
{ return InstructionSet.ARM64_Sve; }

}
break;

Expand Down
3 changes: 3 additions & 0 deletions src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt
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Expand Up @@ -168,6 +168,7 @@ instructionset ,ARM64 , , , ,Dczva
instructionset ,ARM64 , ,Rcpc ,26 ,Rcpc ,rcpc
instructionset ,ARM64 ,VectorT128 , ,39 ,VectorT128 ,vectort128
instructionset ,ARM64 , ,Rcpc2 ,42 ,Rcpc2 ,rcpc2
instructionset ,ARM64 ,Sve , ,43 ,Sve ,sve

instructionset64bit,ARM64 ,ArmBase
instructionset64bit,ARM64 ,AdvSimd
Expand All @@ -177,6 +178,7 @@ instructionset64bit,ARM64 ,Dp
instructionset64bit,ARM64 ,Rdm
instructionset64bit,ARM64 ,Sha1
instructionset64bit,ARM64 ,Sha256
instructionset64bit,ARM64 ,Sve

vectorinstructionset,ARM64,Vector64
vectorinstructionset,ARM64,Vector128
Expand All @@ -191,6 +193,7 @@ implication ,ARM64 ,Sha256 ,ArmBase
implication ,ARM64 ,Vector64 ,AdvSimd
implication ,ARM64 ,Vector128 ,AdvSimd
implication ,ARM64 ,VectorT128 ,AdvSimd
implication ,ARM64 ,Sve ,AdvSimd

; ,name and aliases ,archs ,lower baselines included by implication
;
Expand Down
5 changes: 5 additions & 0 deletions src/coreclr/vm/codeman.cpp
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Expand Up @@ -1511,6 +1511,11 @@ void EEJitManager::SetCpuInfo()
CPUCompileFlags.Set(InstructionSet_Sha256);
}

if (((cpuFeatures & ARM64IntrinsicConstants_Sve) != 0) && CLRConfig::GetConfigValue(CLRConfig::EXTERNAL_EnableArm64Sve))
{
CPUCompileFlags.Set(InstructionSet_Sve);
}

// DCZID_EL0<4> (DZP) indicates whether use of DC ZVA instructions is permitted (0) or prohibited (1).
// DCZID_EL0<3:0> (BS) specifies Log2 of the block size in words.
//
Expand Down
6 changes: 6 additions & 0 deletions src/native/minipal/cpufeatures.c
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Expand Up @@ -34,6 +34,9 @@
#ifndef HWCAP_ASIMDDP
#define HWCAP_ASIMDDP (1 << 20)
#endif
#ifndef HWCAP_SVE
#define HWCAP_SVE (1 << 22)
#endif

#endif

Expand Down Expand Up @@ -356,6 +359,9 @@ int minipal_getcpufeatures(void)
if (hwCap & HWCAP_ASIMDRDM)
result |= ARM64IntrinsicConstants_Rdm;

if (hwCap & HWCAP_SVE)
result |= ARM64IntrinsicConstants_Sve;

#else // !HAVE_AUXV_HWCAP_H

#if HAVE_SYSCTLBYNAME
Expand Down
1 change: 1 addition & 0 deletions src/native/minipal/cpufeatures.h
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Expand Up @@ -57,6 +57,7 @@ enum ARM64IntrinsicConstants
ARM64IntrinsicConstants_Rcpc = 0x0100,
ARM64IntrinsicConstants_VectorT128 = 0x0200,
ARM64IntrinsicConstants_Rcpc2 = 0x0400,
ARM64IntrinsicConstants_Sve = 0x0800,
};

#include <assert.h>
Expand Down