sycl: scalar SWAR byte-subtract in Q6_K MMVQ dot product#22156
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ggerganov merged 2 commits intoMay 18, 2026
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Signed-off-by: Chun Tao <chun.tao@intel.com>
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NeoZhangJianyu
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Could you share the test result of this PR to show the value?
Thank you!
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Here is a subset of test data showing the range of model-dependent improvements. See bold lines for greatest improvement below. Baseline commit is deab41e
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arthw
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arthw
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It's good job!
Thank you very much!
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* master: (100 commits) Agent update hexagon: add support for TRI op (ggml-org#22822) ggml-hexagon: add PAD op HVX kernel (ggml-org#23078) docker : add OCI image labels for version and build date (ggml-org#21653) common : remove hf cache migration (ggml-org#23266) ui: Update KaTeX package and clean up logs from `sass` warnings (ggml-org#23275) feat: add scroll-to-bottom button to chat + prevent forced scroll down (ggml-org#23270) ui: Refactor models store, MCP service, and gate logs behind VITE_DEBUG (ggml-org#23236) ui: Centralize monospace font styles in app.css (ggml-org#23272) webui: fix Tailwind v4 utility classes missing when built via cmake (ggml-org#23253) llama: initialize pre-norm embedding mask flag (ggml-org#23256) add myself to conversion (ggml-org#23261) ci : added kleidiai-server to server-self-hosted workflow (ggml-org#22435) scripts : allow wc2wt with an existing branch (ggml-org#23189) sycl: scalar SWAR byte-subtract in Q6_K MMVQ dot product (ggml-org#22156) sycl: route small f32 matmuls to oneMKL, bypass oneDNN (ggml-org#22150) sycl : fix error when use -mg 1 error (ggml-org#23140) update bid to match each layers MTP source (ggml-org#23237) cmake : do not check for bin install dir (ggml-org#23234) feat: Support d_conv=15 for ssm-conv.cu (ggml-org#23017) ...
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) Signed-off-by: Chun Tao <chun.tao@intel.com> Co-authored-by: Chun Tao <chun.tao@intel.com> (cherry picked from commit 0caf2a1)
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Overview
Authors
Small perf cleanup for Q6_K MMVQ on Intel GPUs.
The Q6_K MMVQ dot product previously called
dpct::vectorized_binary<sycl::char4>(..., dpct::sub_sat())to computea byte-wise saturated subtract in a packed
int. On Intel targets this lowers to a scalarized sequence. Replaces it with a 4-byte SWAR trick (((a | 0x80808080u) - b) ^ 0x80808080u, safe under the known-range inputs) and a straight-line two-lane scalar dot (dp4a × 2) instead of theQR6_K-iterated loop.Applied in all three Q6_K MMVQ sites: the standalone
vec_dot_q6_K_q8_1_impl_mmvq, thereorder_vec_dot_q_sycl<Q6_K>method and operator, and the top-levelvec_dot_q6_K_q8_1.Bitwise equivalent on inputs produced by quantization; no accuracy change. Measurable tg improvement on BMG for Q6_K-heavy models.
Additional information
Split from #22066 per reviewer request for independent review.
Requirements