[SYCL] Support OP XIELU

[atsmith3]

Support XIELU

Overview

Following design patterns in the other back ends to implement the XIELU op in SYCL.

I have tested the XIELU op on Arc Pro B60 and Intel Integrated Graphics.

./test-backend-ops -o XIELU

Results:

Backend 1/4: SYCL0
  Device description: Intel(R) Arc(TM) Pro B60 Graphics
  Device memory: 24480 MB (24399 MB free)

  XIELU(type=f32,ne=[10,5,4,3]): OK
  XIELU(type=f16,ne=[10,5,4,3]): OK
  XIELU(type=f32,ne=[512,16,1,1]): OK
  XIELU(type=f16,ne=[512,16,1,1]): OK
  4/4 tests passed
  Backend SYCL0: OK
Backend 2/4: SYCL1
  Device description: Intel(R) Arc(TM) Pro B60 Graphics
  Device memory: 24480 MB (24416 MB free)

  XIELU(type=f32,ne=[10,5,4,3]): OK
  XIELU(type=f16,ne=[10,5,4,3]): OK
  XIELU(type=f32,ne=[512,16,1,1]): OK
  XIELU(type=f16,ne=[512,16,1,1]): OK
  4/4 tests passed
  Backend SYCL1: OK
Backend 3/4: SYCL2
  Device description: Intel(R) Graphics
  Device memory: 29010 MB (12797 MB free)

  XIELU(type=f32,ne=[10,5,4,3]): OK
  XIELU(type=f16,ne=[10,5,4,3]): OK
  XIELU(type=f32,ne=[512,16,1,1]): OK
  XIELU(type=f16,ne=[512,16,1,1]): OK
  4/4 tests passed
  Backend SYCL2: OK

Requirements

None

• I have read and agree with the contributing guidelines

• AI usage disclosure: YES AI was used to plan, and implement this backend operation. Sonnet 5, ClaudeCode

[arthw]

It's good job!

Thank you!