RISC-V: Add optimized decompression path#236
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RISC-V lacks conditional-move (cmov) instructions, making the x86
cmov-based path suboptimal. Use a branch-based approach similar to
ARM64, and adopt the same ExtractOffset / Load16 strategy.
Benchmarks on RV64 show:
- UFlat/UValidate: +22~26% on text workloads
- UFlatSink: +22~23%
- Binary data (jpg/pdf): no regression
- Compression (ZFlat): unchanged
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This is a copy of #234 |
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Summary
This PR adds a RISC-V-optimized decompression path for the branchless inner loop in Snappy.
RISC-V lacks conditional-move (
cmov) instructions, making the existing x86-optimizedAdvanceToNextTagX86Optimizedsuboptimal on RISC-V platforms.We introduce
AdvanceToNextTagRISCVOptimizedwith a branch structure similar to ARM, and share ARM'sExtractOffset/Load16strategy.Motivation
The decompression loop (
DecompressBranchless) is the hottest path for Snappy'sRawUncompress,Uncompress, and validation APIs.cmovandvolatileloads to minimize latency.csinc.cmovwith extra register moves and branches.This patch gives RISC-V its own optimized path.
Changes Made
AdvanceToNextTagRISCVOptimized()insnappy.ccExtractOffset()to includedefined(__riscv)alongsidedefined(__aarch64__)DecompressBranchless()to use the new RISC-V path withLoad16Implementation Details
#if defined(__riscv)Performance Results
Test Environment
-march=rv64gcvBM_UFlat (Decompression) – Core Improvement
BM_UValidate (Validation) – Consistent Gains
Binary Data – No Regression
Other Operations
Test Repeatability
Three independent runs confirm stable and reproducible results.
All text workloads show consistently +21~23% improvement; binary workloads show <2% variance (within measurement noise).
Compatibility & Portability
__riscvdefined)#if defined(__riscv)Testing
snappy_unittestpasses all testssnappy_benchmarkverified on RISC-V hardware (Banana Pi K1)Checklist
Screenshots
Unit Tests - All Pass

Benchmark - Before Optimization

Benchmark - After Optimization
