Discussions

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  Diff pair routing of connections in blocks

  jfatcl asked Jan 30, 2026 in Q&A · Answered

  

  

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  Adding multiple vias to a track/plane

  jfatcl asked Jan 20, 2026 in Q&A · Unanswered

  

  

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  Create a polygonal padstack: expanding the copper polygon to create the mask

  auxym asked Jan 14, 2026 in Q&A · Answered

  

  

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  How to add parts from other pool in project (eg. from Murata Chip Capacitors pool)

  auxym asked Jan 14, 2026 in Q&A · Closed · Unanswered

  

  

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  Placing PTH on plane (pour) results in copper clearance check fails

  auxym asked Nov 24, 2025 in Q&A · Answered

  

  

  

  

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  Sidebar size.

  eslavko started Nov 12, 2025 in General

  

  

  

  

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  Will survive

  eslavko started Nov 13, 2025 in General

  

  

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  Python module build issue

  tkornack asked Nov 7, 2025 in Q&A · Unanswered

  

  

  

  

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  What about Wayland...

  FabriceSalvaire started Oct 28, 2025 in General

  

  

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  Unable to edit certain elements such as the automatic part labels on the silkscreen layer

  pmjobin asked Oct 18, 2025 in Q&A · Answered

  

  

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  PDF Export

  sam-1647 asked Sep 29, 2025 in Q&A · Unanswered

  

  

  

  

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  Composable parts?

  oldrev asked Mar 13, 2025 in Q&A · Answered

  

  

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  I tried to layout BGA DDR3 with HorizonEDA but failed, here’s what I learned

  oldrev started Mar 4, 2025 in Ideas

  

  

  

  

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  Introduction / Willing to participate / Asking for help beyond the documentation

  ThierryMGTX started Dec 25, 2024 in General

  

  

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  Pool data structure

  nehzatali started Oct 9, 2024 in General

  

  

  

  

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  Electrolytic capacitors

  cgudrian asked Aug 25, 2024 in Q&A · Answered

  

  

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  Visualize trace impedence / crosstalk in board or 3d editor?

  frmdstryr started Jun 18, 2024 in Ideas

  

  

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  Compiling on Ubuntu 24.04

  tkornack started May 11, 2024 in General · Closed

  

  

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  Migrating from Discourse

  carrotIndustries announced Apr 27, 2024 in Announcements

  

  

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