Skip to content

Conversation

@lukaszstolarczuk
Copy link
Contributor

  • fix the issue with missing SYCL path (previously not passed to main.py when regenerating results file)
  • add missing exception handling in main.py
  • use git fetch instead of pull when re-generating results - it's quicker and do not spam logs with redundant refs being pulled

and add better handling in case of any other issues
…esults

it's quicker and do not spam the logs with redundant refs being pulled
@lukaszstolarczuk
Copy link
Contributor Author

@lukaszstolarczuk lukaszstolarczuk marked this pull request as ready for review January 2, 2026 17:20
@lukaszstolarczuk lukaszstolarczuk requested a review from a team as a code owner January 2, 2026 17:20
Copy link
Contributor

@lslusarczyk lslusarczyk left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

ok, looks good, I assume you ran it and it works

@lslusarczyk
Copy link
Contributor

@intel/llvm-gatekeepers , please merge

@kswiecicki kswiecicki merged commit 92b2665 into intel:sycl Jan 5, 2026
15 checks passed
@lukaszstolarczuk lukaszstolarczuk deleted the fix-bench-ci branch January 5, 2026 10:27
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants