Pipelined RISC processor implementation on Altera DE2

Designed and Implemented one Pipelined RISC processor that has HW-based data hazard resolution mechanisms, a static branch predictor and set-associative instruction/data caches on Altera DE2 FPGA Board.

About

This is the course project cooperated with Pan Yi in CSCE830 - Computer Architecture (Spring 2012, instructor, Dr Jiang).

Contribution

1. Pipeline: designed 5-stage pipeline RISC processor.
2. Data hazard resolution: detect data hazard and forward data
3. Caches: 2-way set-associative instruction/data caches, including performance counters.
4. Static branch predictor: mitigate the control hazard.