💻 Green-RISC 🥬

    🕹️ Minimal implementation of a 5 stage pipelined 32 bit RISC V CPU in verilog

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Types of instructions in RISC-V arch

Vector table for determining the type of instruction based on the instr value

Immediate values decode table (expect for a R instr)

Few Opcodes (instr[30] + func3 + opcode ) for different instruction

Overall arch of the CPU implementation