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Pull requests: llvm/circt

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Pull requests list

Bump LLVM
#10542 opened May 25, 2026 by uenoku Member • Draft
1
[LTL] Add ClockedAtomOp description
#10541 opened May 24, 2026 by Clo91eaf Contributor Loading…
3
Add BMCTrace runtime support and unit tests for text counterexample formatting
#10537 opened May 23, 2026 by 5iri Contributor Loading…
[SimToSV] Fix an error occurred when a sim.pause is nested in a scf.if
#10535 opened May 23, 2026 by nanjo712 Contributor Loading…
1
9
[Sim] Add pass for converting sim.triggered to hw.triggered
#10534 opened May 23, 2026 by nanjo712 Contributor Loading…
12
[FIRRTLToHW] Remove the SYNTHESIS guard in printf/flush lowering path
#10526 opened May 22, 2026 by nanjo712 Contributor Loading…
9
[Arc] Add coroutine ops Arc Involving the `arc` dialect
#10522 opened May 21, 2026 by fabianschuiki Contributor Loading…
5
[Moore][ImportVerilog][MooreToCore][Sim] Add $fdisplay and $fwrite ImportVerilog
#10520 opened May 21, 2026 by VecoMr Contributor Loading…
2
[FIRRTL] EliminateWires: preserve sv.attributes when converting WireOp to NodeOp
#10519 opened May 21, 2026 by bheneffe Loading…
12
[Synth] Add SAT-based exact synthesis pass
#10493 opened May 18, 2026 by uenoku Member Loading…
1
[circt-lec] Lower truth tables before SMT conversion
#10491 opened May 17, 2026 by uenoku Member Loading…
1
Bump slang 11.0
#10488 opened May 16, 2026 by mi-and-core • Draft
1
[SV] Add pass to hide non-synthesizable ops SV System Verilog Dialect
#10479 opened May 15, 2026 by teqdruid Contributor Loading…
1
5
[ImportVerilog] Preserve declaration order across regular and interface-modport ports
#10468 opened May 14, 2026 by micprog Contributor Loading…
15
[HW] Add forceable wire support with HW RefType
#10447 opened May 12, 2026 by prithayan Contributor • Draft
[DRAFT][FIRRTLToHW] Emit sim.proc.print instead of sim.print
#10441 opened May 12, 2026 by nanjo712 Contributor • Draft
Add results to sv.ifdef
#10436 opened May 12, 2026 by prithayan Contributor • Draft
2
[Sim] Extract common logic of ProceduralizeSim for reuse
#10422 opened May 9, 2026 by nanjo712 Contributor Loading…
6
[FIRRTL] Add mux2cell/mux4cell canonicalization patterns
#10414 opened May 8, 2026 by anaumchev Loading…
2
1
[debug][firrtl] Carry Chisel source-level types through the pipeline
#10410 opened May 7, 2026 by fkhaidari Loading…
3
[HW] HWVectorization Part 4: Partial Vectorization (Chunking)
#10399 opened May 6, 2026 by mafeguimaraes Contributor Loading…
[Support] Add parallel instance graph visitors
#10353 opened Apr 29, 2026 by seldridge Member • Draft
4
[ImportVerilog] Support use-before-declare across module bodies
#10350 opened Apr 28, 2026 by AmurG Contributor Loading…
11
[FIRRTL] LowerLayers: Inline enabled layers FIRRTL Involving the `firrtl` dialect
#10348 opened Apr 28, 2026 by rwy7 Contributor Loading…
4
fix: update flattenIndices to generate correct indices for a flattened memref
#10327 opened Apr 25, 2026 by Abhilekhgautam Loading…
1
6
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