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Add support for NMIs to ot_earlgrey #111

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10d4825
[ot] hw/opentitan: ot_aon_timer: Make wakeup timer 64 bits
AlexJones0 Jan 7, 2025
b29e416
[ot] hw/riscv: ot_earlgrey: Connect device alerts to alert handler
AlexJones0 Jan 16, 2025
764d881
[ot] hw/riscv: ot_earlgrey: Connect alert escalation severities
AlexJones0 Jan 21, 2025
b3e8936
[ot] hw/opentitan: Use QEMU IRQs instead of Ibex IRQs for alerts
AlexJones0 Jan 18, 2025
a7079c0
[ot] target/riscv: Add support for Non-Maskable Interrupts
AlexJones0 Jan 21, 2025
26878e3
[ot] hw/opentitan: ot_ibex_wrapper: Add NMI support to Ibex Wrapper
AlexJones0 Jan 21, 2025
3c35b08
[ot] hw/opentitan: ot_ibex_wrapper: Make NMI registers rw1s/rw1c
AlexJones0 Jan 21, 2025
70bde01
[ot] hw/riscv: ot_earlgrey: Set NMI mcause for Ibex to 31
AlexJones0 Jan 21, 2025
3daef7b
[ot] hw/opentitan: ot_aon_timer: Connect watchdog bark NMI
AlexJones0 Jan 21, 2025
650257a
[ot] hw/opentitan: ot_alert: Connect alert phase 0 NMI
AlexJones0 Jan 21, 2025
7ab767a
[ot] hw/intc: Only clear pending IRQs at PLIC when claimed
AlexJones0 Jan 21, 2025
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[ot] hw/riscv: ot_earlgrey: Connect device alerts to alert handler 
Connect the alerts for each of the OpenTitan Earlgrey devices to the
alert handler. This is based on the mappings found in the autogenerated
`hw/top_earlgrey/sw/autogen/top_earlgrey.h` file for the Earlgrey top
found in the OpenTitan repository.

Signed-off-by: Alex Jones <alex.jones@lowrisc.org>
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@AlexJones0
AlexJones0 committed Jan 22, 2025
commit b29e41686944b4dcc96ac0fdb8b047a646f68745
127 changes: 101 additions & 26 deletions hw/riscv/ot_earlgrey.c
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Original file line number Diff line number Diff line change
Expand Up @@ -212,6 +212,14 @@ static const uint32_t ot_eg_pmp_addrs[] = {
#define OT_EG_SOC_GPIO_SYSBUS_IRQ(_irq_, _target_, _num_) \
IBEX_GPIO_SYSBUS_IRQ(_irq_, OT_EG_SOC_DEV_##_target_, _num_)

#define OT_EG_SOC_GPIO_ALERT(_snum_, _tnum_) \
OT_EG_SOC_SIGNAL(OT_DEVICE_ALERT, _snum_, ALERT_HANDLER, OT_DEVICE_ALERT, \
_tnum_)

#define OT_EG_SOC_GPIO_ESCALATE(_snum_, _tgt_, _tnum_) \
OT_EG_SOC_SIGNAL(OT_ALERT_ESCALATE, _snum_, _tgt_, OT_ALERT_ESCALATE, \
_tnum_)

#define OT_EG_SOC_DEVLINK(_pname_, _target_) \
IBEX_DEVLINK(_pname_, OT_EG_SOC_DEV_##_target_)

Expand Down Expand Up @@ -340,7 +348,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
OT_EG_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 6),
OT_EG_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 7),
OT_EG_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 8),
OT_EG_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 9)
OT_EG_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 9),
OT_EG_SOC_GPIO_ALERT(0, 0)
),
.prop = IBEXDEVICEPROPDEFS(
IBEX_DEV_UINT_PROP("pclk", OT_EG_PERIPHERAL_CLK_HZ)
Expand All @@ -362,7 +371,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
OT_EG_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 15),
OT_EG_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 16),
OT_EG_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 17),
OT_EG_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 18)
OT_EG_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 18),
OT_EG_SOC_GPIO_ALERT(0, 1)
),
.prop = IBEXDEVICEPROPDEFS(
IBEX_DEV_UINT_PROP("pclk", OT_EG_PERIPHERAL_CLK_HZ)
Expand All @@ -384,7 +394,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
OT_EG_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 24),
OT_EG_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 25),
OT_EG_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 26),
OT_EG_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 27)
OT_EG_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 27),
OT_EG_SOC_GPIO_ALERT(0, 2)
),
.prop = IBEXDEVICEPROPDEFS(
IBEX_DEV_UINT_PROP("pclk", OT_EG_PERIPHERAL_CLK_HZ)
Expand All @@ -406,7 +417,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
OT_EG_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 33),
OT_EG_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 34),
OT_EG_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 35),
OT_EG_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 36)
OT_EG_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 36),
OT_EG_SOC_GPIO_ALERT(0, 3)
),
.prop = IBEXDEVICEPROPDEFS(
IBEX_DEV_UINT_PROP("pclk", OT_EG_PERIPHERAL_CLK_HZ)
Expand Down Expand Up @@ -449,7 +461,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
OT_EG_SOC_GPIO_SYSBUS_IRQ(28, PLIC, 65),
OT_EG_SOC_GPIO_SYSBUS_IRQ(29, PLIC, 66),
OT_EG_SOC_GPIO_SYSBUS_IRQ(30, PLIC, 67),
OT_EG_SOC_GPIO_SYSBUS_IRQ(31, PLIC, 68)
OT_EG_SOC_GPIO_SYSBUS_IRQ(31, PLIC, 68),
OT_EG_SOC_GPIO_ALERT(0, 4)
)
},
[OT_EG_SOC_DEV_SPI_DEVICE] = {
Expand All @@ -466,7 +479,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
OT_EG_SOC_GPIO_SYSBUS_IRQ(4, PLIC, 73),
OT_EG_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 74),
OT_EG_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 75),
OT_EG_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 76)
OT_EG_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 76),
OT_EG_SOC_GPIO_ALERT(0, 5)
),
},
[OT_EG_SOC_DEV_I2C0] = {
Expand Down Expand Up @@ -520,7 +534,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
),
.gpio = IBEXGPIOCONNDEFS(
OT_EG_SOC_GPIO(0, HART, IRQ_M_TIMER),
OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 124)
OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 124),
OT_EG_SOC_GPIO_ALERT(0, 10)
),
.prop = IBEXDEVICEPROPDEFS(
IBEX_DEV_UINT_PROP("pclk", OT_EG_PERIPHERAL_CLK_HZ)
Expand All @@ -534,7 +549,12 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
),
.gpio = IBEXGPIOCONNDEFS(
OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 125),
OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 126)
OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 126),
OT_EG_SOC_GPIO_ALERT(0, 11),
OT_EG_SOC_GPIO_ALERT(1, 12),
OT_EG_SOC_GPIO_ALERT(2, 13),
OT_EG_SOC_GPIO_ALERT(3, 14),
OT_EG_SOC_GPIO_ALERT(4, 15)
),
.link = IBEXDEVICELINKDEFS(
OT_EG_SOC_DEVLINK("edn", EDN0),
Expand Down Expand Up @@ -573,7 +593,10 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
{ .base = 0x40140000u }
),
.gpio = IBEXGPIOCONNDEFS(
OT_EG_SOC_RSP(OT_PWRMGR_LC, PWRMGR)
OT_EG_SOC_RSP(OT_PWRMGR_LC, PWRMGR),
OT_EG_SOC_GPIO_ALERT(0, 16),
OT_EG_SOC_GPIO_ALERT(1, 17),
OT_EG_SOC_GPIO_ALERT(2, 18)
),
.link = IBEXDEVICELINKDEFS(
OT_EG_SOC_DEVLINK("otp_ctrl", OTP_CTRL),
Expand Down Expand Up @@ -633,7 +656,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
),
.gpio = IBEXGPIOCONNDEFS(
OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 131),
OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 132)
OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 132),
OT_EG_SOC_GPIO_ALERT(0, 19)
),
.prop = IBEXDEVICEPROPDEFS(
IBEX_DEV_UINT_PROP("bus-num", 0)
Expand All @@ -646,7 +670,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
),
.gpio = IBEXGPIOCONNDEFS(
OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 133),
OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 134)
OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 134),
OT_EG_SOC_GPIO_ALERT(0, 20)
),
.prop = IBEXDEVICEPROPDEFS(
IBEX_DEV_UINT_PROP("bus-num", 1)
Expand Down Expand Up @@ -678,7 +703,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
OT_IBEX_WRAPPER_CPU_EN,
OT_IBEX_PWRMGR_CPU_EN),
OT_EG_SOC_SIGNAL(OT_PWRMGR_RST_REQ, 0, RSTMGR,
OT_RSTMGR_RST_REQ, 0)
OT_RSTMGR_RST_REQ, 0),
OT_EG_SOC_GPIO_ALERT(0, 22)
),
.prop = IBEXDEVICEPROPDEFS(
IBEX_DEV_UINT_PROP("num-rom", 1u),
Expand All @@ -692,14 +718,20 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
),
.gpio = IBEXGPIOCONNDEFS(
OT_EG_SOC_SIGNAL(OT_RSTMGR_SW_RST, 0, PWRMGR, \
OT_PWRMGR_SW_RST, 0)
OT_PWRMGR_SW_RST, 0),
OT_EG_SOC_GPIO_ALERT(0, 23),
OT_EG_SOC_GPIO_ALERT(1, 24)
),
},
[OT_EG_SOC_DEV_CLKMGR] = {
.type = TYPE_OT_CLKMGR,
.memmap = MEMMAPENTRIES(
{ .base = 0x40420000u }
),
.gpio = IBEXGPIOCONNDEFS(
OT_EG_SOC_GPIO_ALERT(0, 25),
OT_EG_SOC_GPIO_ALERT(1, 26)
)
},
[OT_EG_SOC_DEV_SYSRST_CTRL] = {
.type = TYPE_UNIMPLEMENTED_DEVICE,
Expand Down Expand Up @@ -739,6 +771,9 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
.memmap = MEMMAPENTRIES(
{ .base = 0x40460000u }
),
.gpio = IBEXGPIOCONNDEFS(
OT_EG_SOC_GPIO_ALERT(0, 30)
)
},
[OT_EG_SOC_DEV_AON_TIMER] = {
.type = TYPE_OT_AON_TIMER,
Expand All @@ -751,7 +786,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
OT_EG_SOC_SIGNAL(OT_AON_TIMER_WKUP, 0, PWRMGR, \
OT_PWRMGR_WKUP, OT_PWRMGR_WAKEUP_AON_TIMER),
OT_EG_SOC_SIGNAL(OT_AON_TIMER_BITE, 0, PWRMGR, \
OT_PWRMGR_RST, OT_EG_RESET_AON_TIMER)
OT_PWRMGR_RST, OT_EG_RESET_AON_TIMER),
OT_EG_SOC_GPIO_ALERT(0, 31)
),
.prop = IBEXDEVICEPROPDEFS(
IBEX_DEV_UINT_PROP("pclk", OT_EG_AON_CLK_HZ)
Expand All @@ -768,13 +804,20 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
.memmap = MEMMAPENTRIES(
{ .base = 0x40490000u }
),
.gpio = IBEXGPIOCONNDEFS(
OT_EG_SOC_GPIO_ALERT(0, 32),
OT_EG_SOC_GPIO_ALERT(1, 33)
)
},
[OT_EG_SOC_DEV_SRAM_RET_CTRL] = {
.type = TYPE_OT_SRAM_CTRL,
.memmap = MEMMAPENTRIES(
{ .base = 0x40500000u },
{ .base = 0x40600000u }
),
.gpio = IBEXGPIOCONNDEFS(
OT_EG_SOC_GPIO_ALERT(0, 34)
),
.link = IBEXDEVICELINKDEFS(
OT_EG_SOC_DEVLINK("otp_ctrl", OTP_CTRL)
),
Expand All @@ -797,7 +840,12 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 162),
OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 163),
OT_EG_SOC_GPIO_SYSBUS_IRQ(4, PLIC, 164),
OT_EG_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 165)
OT_EG_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 165),
OT_EG_SOC_GPIO_ALERT(0, 35),
OT_EG_SOC_GPIO_ALERT(1, 36),
OT_EG_SOC_GPIO_ALERT(2, 37),
OT_EG_SOC_GPIO_ALERT(3, 38),
OT_EG_SOC_GPIO_ALERT(4, 39)
),
},
[OT_EG_SOC_DEV_AES] = {
Expand All @@ -806,7 +854,9 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
{ .base = 0x41100000u }
),
.gpio = IBEXGPIOCONNDEFS(
OT_EG_SOC_CLKMGR_HINT(OT_CLKMGR_HINT_AES)
OT_EG_SOC_CLKMGR_HINT(OT_CLKMGR_HINT_AES),
OT_EG_SOC_GPIO_ALERT(0, 42),
OT_EG_SOC_GPIO_ALERT(1, 43)
),
.link = IBEXDEVICELINKDEFS(
OT_EG_SOC_DEVLINK("edn", EDN0)
Expand All @@ -824,7 +874,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 166),
OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 167),
OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 168),
OT_EG_SOC_CLKMGR_HINT(OT_CLKMGR_HINT_HMAC)
OT_EG_SOC_CLKMGR_HINT(OT_CLKMGR_HINT_HMAC),
OT_EG_SOC_GPIO_ALERT(0, 44)
),
},
[OT_EG_SOC_DEV_KMAC] = {
Expand All @@ -835,7 +886,9 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
.gpio = IBEXGPIOCONNDEFS(
OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 169),
OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 170),
OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 171)
OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 171),
OT_EG_SOC_GPIO_ALERT(0, 45),
OT_EG_SOC_GPIO_ALERT(1, 46)
),
.link = IBEXDEVICELINKDEFS(
OT_EG_SOC_DEVLINK("edn", EDN0)
Expand All @@ -852,7 +905,9 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
),
.gpio = IBEXGPIOCONNDEFS(
OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 172),
OT_EG_SOC_CLKMGR_HINT(OT_CLKMGR_HINT_OTBN)
OT_EG_SOC_CLKMGR_HINT(OT_CLKMGR_HINT_OTBN),
OT_EG_SOC_GPIO_ALERT(0, 47),
OT_EG_SOC_GPIO_ALERT(1, 48)
),
.link = IBEXDEVICELINKDEFS(
OT_EG_SOC_DEVLINK("edn-u", EDN0),
Expand Down Expand Up @@ -884,7 +939,9 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 174),
OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 175),
OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 176),
OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 177)
OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 177),
OT_EG_SOC_GPIO_ALERT(0, 51),
OT_EG_SOC_GPIO_ALERT(1, 52)
),
.link = IBEXDEVICELINKDEFS(
OT_EG_SOC_DEVLINK("random_src", ENTROPY_SRC),
Expand All @@ -900,7 +957,9 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 178),
OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 179),
OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 180),
OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 181)
OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 181),
OT_EG_SOC_GPIO_ALERT(0, 53),
OT_EG_SOC_GPIO_ALERT(1, 54)
),
.link = IBEXDEVICELINKDEFS(
OT_EG_SOC_DEVLINK("ast", AST),
Expand All @@ -914,7 +973,9 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
),
.gpio = IBEXGPIOCONNDEFS(
OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 182),
OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 183)
OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 183),
OT_EG_SOC_GPIO_ALERT(0, 55),
OT_EG_SOC_GPIO_ALERT(1, 56)
),
.link = IBEXDEVICELINKDEFS(
OT_EG_SOC_DEVLINK("csrng", CSRNG)
Expand All @@ -930,7 +991,9 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
),
.gpio = IBEXGPIOCONNDEFS(
OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 184),
OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 185)
OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 185),
OT_EG_SOC_GPIO_ALERT(0, 57),
OT_EG_SOC_GPIO_ALERT(1, 58)
),
.link = IBEXDEVICELINKDEFS(
OT_EG_SOC_DEVLINK("csrng", CSRNG)
Expand All @@ -945,6 +1008,9 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
{ .base = 0x411c0000u },
{ .base = 0x10000000u }
),
.gpio = IBEXGPIOCONNDEFS(
OT_EG_SOC_GPIO_ALERT(0, 59)
),
.link = IBEXDEVICELINKDEFS(
OT_EG_SOC_DEVLINK("otp_ctrl", OTP_CTRL)
),
Expand All @@ -964,7 +1030,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
OT_EG_SOC_SIGNAL(OT_ROM_CTRL_GOOD, 0, PWRMGR, \
OT_PWRMGR_ROM_GOOD, 0),
OT_EG_SOC_SIGNAL(OT_ROM_CTRL_DONE, 0, PWRMGR, \
OT_PWRMGR_ROM_DONE, 0)
OT_PWRMGR_ROM_DONE, 0),
OT_EG_SOC_GPIO_ALERT(0, 60)
),
.link = IBEXDEVICELINKDEFS(
OT_EG_SOC_DEVLINK("kmac", KMAC)
Expand All @@ -983,6 +1050,12 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
.memmap = MEMMAPENTRIES(
{ .base = 0x411f0000u }
),
.gpio = IBEXGPIOCONNDEFS(
OT_EG_SOC_GPIO_ALERT(0, 61),
OT_EG_SOC_GPIO_ALERT(1, 62),
OT_EG_SOC_GPIO_ALERT(2, 63),
OT_EG_SOC_GPIO_ALERT(3, 64)
),
.link = IBEXDEVICELINKDEFS(
OT_EG_SOC_DEVLINK("edn", EDN0)
),
Expand All @@ -1000,7 +1073,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
OT_EG_SOC_DM_CONNECTION(OT_EG_SOC_DEV_DM, 0),
OT_EG_SOC_DM_CONNECTION(OT_EG_SOC_DEV_DM, 1),
OT_EG_SOC_DM_CONNECTION(OT_EG_SOC_DEV_DM, 2),
OT_EG_SOC_DM_CONNECTION(OT_EG_SOC_DEV_DM, 3)
OT_EG_SOC_DM_CONNECTION(OT_EG_SOC_DEV_DM, 3),
OT_EG_SOC_GPIO_ALERT(0, 40)
),
},
[OT_EG_SOC_DEV_PLIC] = {
Expand Down Expand Up @@ -1032,7 +1106,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
{ .base = 0x2c000000u }
),
.gpio = IBEXGPIOCONNDEFS(
OT_EG_SOC_GPIO(0, HART, IRQ_M_SOFT)
OT_EG_SOC_GPIO(0, HART, IRQ_M_SOFT),
OT_EG_SOC_GPIO_ALERT(0, 41)
),
},
/* clang-format on */
Expand Down