10 simple memory instructions ld st lld

[mathish06]

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[Copilot]

Pull request overview

Implements Corewar memory instructions (ld, st, lld) and wires them into the VM execution flow.

Changes:

• Added memory instruction handlers and included them in the build.
• Updated instruction dispatch to execute opcodes 2, 3, and 13.
• Adjusted shared operand-reading logic for lld indirect addressing.

Reviewed changes

Copilot reviewed 7 out of 7 changed files in this pull request and generated 5 comments.

Show a summary per file

File	Description
src/instructions/instructions_mem.c	Adds ld, st, and lld implementations.
src/instructions/instructions_calc.c	Exposes get_val and changes indirect addressing behavior for lld.
src/instructions/basic_instructions.c	Moves/adds op_add implementation.
src/core/execute_processes.c	Registers memory instructions in the opcode dispatch table.
src/core/game_loop.c	Changes cycle verification from equality to greater-than-or-equal.
Makefile	Adds the new memory instruction source file to the build.
include/corewar.h	Declares new memory instruction handlers and get_val.

Comments suppressed due to low confidence (5)

src/instructions/instructions_mem.c:53

• st does not validate that the first operand is a valid source register before computing val. If the coding byte or register number is invalid, get_val can return 0 or read another operand type and the handler may still overwrite the destination register/memory.

    decode_coding_byte(vm->arena[(proc->pc + 1) % MEM_SIZE], types);
    val = get_val(vm, proc, types[0], &pos);
    if (types[1] == T_REG) {

src/instructions/instructions_mem.c:74

• lld has the same missing operand validation as ld: it accepts whatever types are decoded instead of enforcing direct/indirect plus register from op_tab. Malformed coding bytes can therefore update registers with values from invalid operand layouts.

    decode_coding_byte(vm->arena[(proc->pc + 1) % MEM_SIZE], types);
    val = get_val(vm, proc, types[0], &pos);
    reg = vm->arena[pos % MEM_SIZE] - 1;

src/instructions/instructions_mem.c:43

• This new st handler is not covered by the existing instruction tests. Please add tests for register destinations, indirect memory writes, invalid source/destination registers, and address wraparound to validate the new store behavior.

void op_st(global_t *global, vm_t *vm, process_t *proc)

src/instructions/instructions_mem.c:64

• This new lld handler is not covered by the instruction test suite. Please add tests that distinguish it from ld, especially indirect addressing without IDX_MOD, carry updates, invalid registers, and memory wraparound.

void op_lld(global_t *global, vm_t *vm, process_t *proc)

src/instructions/instructions_mem.c:57

• When the second st operand decodes to an unsupported type (for example T_DIR), neither branch consumes that operand before proc->pc is updated. The process will resume in the middle of the malformed instruction instead of advancing past the bytes described by the coding byte.

    if (types[1] == T_REG) {
        reg = vm->arena[pos % MEM_SIZE] - 1;
        if (reg >= 0 && reg < REG_NUMBER)
            proc->registers[reg] = val;
        pos += 1;

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