mudler · localai-bot · Aug 6, 2026
diff --git a/.agents/NOW.md b/.agents/NOW.md
@@ -22,9 +22,9 @@ checkpoint on `upstream/main` at `59674cf1d`.
 | Kimi-Linear-48B (KDA+NoPE-MLA+MoE) | **Full-model GB10 e2e RUNS** (bf16-resident §13): CPU+CUDA 13/13·656, no OOM. **Token gate NEAR-TIE 106/128** (6/8 token-exact) | device GDN/MLA islands + bf16 stream; 1.59 tok/s; default OFF |
 | 35B fresh grid | **BOUND** @`1ea26427`: tput 0.93-1.03x, c16 0.93x. INTAKE + Option A both **RESOLVED NEGATIVE** (H2D-out-of-capture tput WASH) | Real lever left: prefill glue (task #61) |
 | Qwen3.5-4B revalidation | 0.9971x @`59674cf1` (#35); TTFT/PSS pass, TPOT/ITL open | `docs/bench-evidence/` |
-| MXFP4 parity (Qwen3-8B) | **Closers binding x3 (`QUANT-CT-MXFP4-CLOSERS`): c1 1.005 PASSES, c2-c8 0.925/0.939/0.953 BELOW, mem 2.18x WIN, gate NO. Byte-exact bitdiff=0, #44 3/3** | c8 same-tool diff → goal row |
+| MXFP4 parity (Qwen3-8B) | **`MARLIN-STRUCT`: decode-graph + gate_up FUSION default-ON (marlin 180→144 GEMM/step = vLLM-structural); #44 3/3, 0.6B/4B 184/184, 32B-NVFP4A16 142/142** | residual = marlin CTA + flash |
 | ROW-SERVE-ASYNC-DENSE-MIRROR | **LANDED+dgx-VERIFIED** (`f9c969ae`): #31 async mirror on classic dense Qwen3; gate RED→GREEN, SACRED 184/184 | Residual: sibling scope one-liner |
-| MXFP4 parity goal | c8 same-tool diff (`QUANT-CT-MXFP4-C8-DIFF`) SETTLES #50: marlin grouped-5-GEMM (gate_up unfused, 180 vs 144) DOMINANT +0.9/+1.4ms; eager gap +0.88ms graph-closeable nets +1.3%; flash same-grid +11% | NEXT: grouped→dense-direct + gate_up fuse |
+| MXFP4 parity goal | graph+fuse default-ON. c8 residual: marlin CTA 144 vs 48 = DOMINANT +1,177us (`VT_MARLIN_E1_PAR1` opt-in → near-parity, but flips strict 32B token → default-OFF), flash +784, glue +195 | NEXT: dense-template marlin port + full binding (oracle) |
 
 In-flight branches (gated default-OFF, not pushed): `laguna-fp4proj-prod`
 (fp4 opt-in), laguna bf16/legacy/pipeline-gemv, `ds4-hc-expand-fuse`.

diff --git a/.agents/benchmark-record.md b/.agents/benchmark-record.md
@@ -12662,3 +12662,36 @@ Tertiary = flash same-kernel/IDENTICAL-grid +11% (KV/splitkv), glue Inductor-fus
 Evidence dgx:~/mxfp4-nsys/{kern_sum_c8_dflt,vllm_offline_kern_c8,kern_sum_c8_graph}.txt +
 gpu_trace_c8_{dflt,graph}/vllm_offline_trace_c8_cuda_gpu_trace.csv + analyze_decode.py/gap_and_shape.py.
 Box left clean (both locks free, GPU idle, worker down, disk 20G, tmux gone).
+
+### QUANT-CT-MXFP4-MARLIN-STRUCT (2026-08-09) — decode-graph + gate_up FUSION default-ON, E=1 par=1 arbiter
+
+Base `origin/main` `027af9b0` (#52). GB10 sm_121a Release, build in `/dev/shm/vc-mxfp4`. Same-tool
+nsys `--cuda-graph-trace=node` c8 decode-window (24×128, M=8-pinned, 235 steady steps, `analyze_decode.py`);
+vLLM side reused from #52 (same pin `55596792`). ours-default = graph+fuse (par1 OFF); ours+par1 = opt-in.
+
+| class | ours-dflt us/step (calls) | ours+par1 | vLLM us/step (calls) | dflt gap | par1 gap |
+|-------|--------------------------:|----------:|---------------------:|---------:|---------:|
+| marlin | 17,463 (144) | 16,512 | 16,286 (144) | +1,177 | +226 |
+| flash  |  6,413 (36)  |  6,436 |  5,629 (36)  | +784   | +807  |
+| glue   |    866 (255) |    869 |    671 (299) | +195   | +198  |
+| lm_head|  5,387       |  5,398 |  5,395       | ~0     | ~0    |
+| BUSY   | 30,431       | 29,510 | 28,190       | +2,241 | +1,320 |
+| GAP    |    297 (1.0%)|    293 |    304 (1.1%) | ~0     | ~0    |
+| SPAN   | 30,732       | 29,800 | 28,491       | +2,241 | +1,309 |
+| TPOT ms (client, nsys-inflated) | 37.22 | 36.23 | 34.58 | +2.64 | +1.65 |
+
+FINDINGS: (1) gate_up FUSION drops modal marlin 180→**144 GEMM/step** (vLLM-structural parity) but only
+−200us marlin — the count was cheap (fused 2N GEMM reads the same weight bytes as 2 narrow, W4A16
+memory-bound); step 2 = structural/correctness parity, not a speed win. (2) At MATCHED 144-count ours
+marlin is 121.3us/call vs vLLM 113.1 = **+7.2%/call = +1,177us = the DOMINANT residual** — the CTA count
+(ours 144 = sms×par3, vLLM dense 48 = sms×1, `blocks = sms*blocks_per_sm` marlin_mm_moe.cu:494), REFUTING
+#52's "per-call near-parity". (3) `VT_MARLIN_E1_PAR1=1` clamp (48 CTAs) recovers 951/1177us (marlin +226
+near-parity, TPOT −0.99ms), token-exact on 8B-MXFP4 (#44 3/3) — MEASURABLY SUFFICIENT, no dense-port
+needed — but flips a strict 32B-NVFP4 token (fp32-reduce regroup, `test_qwen3_32b_nvfp4a16` REQUIRE :344;
+isolated: baseline 142/142, graph-only 142/142, par1-only 59/60) ⇒ default-OFF opt-in; byte-preserving CTA
+reduction = the dense-template marlin port (#50 NO-GO), scoped. Post-par1 the DOMINANT residual is FLASH
+(+807, same kernel+grid, unresolved), then glue (+198, portable-fusion). Full strict binding ratio table
+(c1..c8 x3, fresh oracle) DEFERRED — the strict harness needs an on-REAL-disk RelWithDebInfo build (tmpfs
+fails the mincore cache-drop) + the vLLM oracle whose host-RAM reservation alongside the 27G tmpfs tree is
+the GB10 OOM-reboot risk. Evidence dgx:~/mxfp4-nsys/{oursfused_c8,ourspar1_c8}.nsys-rep, kern_sum_oursfused_c8.txt,
+gpu_trace_{oursfused,ourspar1}_c8_*.csv; gates ~/{gate2,gate4,gate5,iso32b,step1_gate,step1_smoke}.log.
diff --git a/.agents/state.md b/.agents/state.md
@@ -37258,3 +37258,76 @@ kern_sum_c8_dflt.txt, vllm_offline_kern_c8.txt, kern_sum_c8_graph.txt; trace CSV
 gpu_trace_c8_{dflt,graph}_cuda_gpu_trace.csv, vllm_offline_trace_c8_cuda_gpu_trace.csv; analyzers
 analyze_decode.py + gap_and_shape.py; vLLM offline capture nsys_vllm_c8_v2.sh/run_vllm_offline_nsys.sh.
 
+## QUANT-CT-MXFP4-MARLIN-STRUCT: decode-graph default-ON + MXFP4 gate_up FUSION default-ON (180->144 GEMM/step, vLLM-structural) + E=1 CTA-parity par=1 opt-in (arbiter: marlin near-parity, 32B-strict-blocked from default); 4 gated GB10 SHAs
+<!-- state: 2026-08-09T16:00 -->
+
+Closes the #52 marlin-structural + decode-graph levers on `row/QUANT-CT-MXFP4-MARLIN-STRUCT`
+(base `origin/main` `027af9b0`/#52). Build in `/dev/shm/vc-mxfp4` (root disk at floor),
+Release sm_121a CUDA 13.0 `-Werror` clean, all 5 rebuilds EXIT=0. Box left clean (locks
+free, worker down, tmux gone). Three landed changes + one measured opt-in.
+
+STEP 1 — DECODE-GRAPH DEFAULT FLIP (parity-enabler). `DenseDecodeGraphEnabled()`
+(qwen3.cpp) flipped DEFAULT OFF->ON (`VLLM_CPP_QWEN3_DENSE_DECODE_GRAPH=0` opts out; the
+framework `VLLM_CPP_CUDAGRAPH=0` still forces eager inside `Impl::enabled`). Gated on the
+UNMODIFIED #52 binary first (graph env ON vs OFF, capture-safety): `test_qwen3_paged_engine`
+184/184 IDENTICAL ON==OFF (Qwen3-0.6B near-tie + 4B), `test_qwen3_dense_async_serving` 82/82
+IDENTICAL, #44 MXFP4-8B smoke 3/3 token-exact + coherent graph-ON == graph-OFF. Re-verified
+at the flipped default (no env): 184/184 + 82/82 + smoke 3/3. Also clean on the 64-layer
+Qwen3-32B-NVFP4A16 SACRED (graph-only arm 142/142). Banks the #52 measured +1.3% TPOT@c8
+(eager gap 1,184->297us via graph replay) for EVERY classic-dense model (5 registrations).
+
+STEP 2 — MXFP4 gate_up FUSION default-ON (the cheaper structural half). `GateUpFusedEligible`/
+`BuildMarlinDensePairResident`/`GateUpFusedMarlinD` (dense_nvfp4_gemm.h) generalized from
+NVFP4-only to MXFP4 (group_size 16->16|32, `MarlinProcessExpertScalesMxfp4` E8M0 passthrough
++ g=1.0, `margs.mxfp4/group_size`); `!gw.is_mxfp4` exclusion dropped, replaced by
+`is_mxfp4==is_mxfp4 && group_size==group_size`. MEASURED (same-tool nsys, ours default): the
+classic-dense Qwen3-8B-MXFP4 decode now launches **modal marlin/step = 144** (4/layer: qkv,
+o, down + FUSED gate_up), down from #52's 180 (5/layer, gate_up split) — STRUCTURAL parity
+with vLLM's 144. Byte-token-exact: `test_linear_method` new unit (fused ~= split, 99.9%
+bit-exact — the fp32 split-K reduce regroups [2N,K] vs [N,K] by 1 bf16 ULP, silu-amplified on
+random OOD inputs, so the bar is bit-exact-FRACTION >=99% not byte, RED-first: pre-wire mxfp4
+misread group-32 E8M0 as group-16 fp8-e4m3 -> ~all wrong) + fused-path-ran counter; #44 smoke
+FUSED 3/3 == SPLIT (`VT_MOE_FUSED_W13=0`) both token-exact; 32B-NVFP4 (already fused pre-change)
+142/142. SPEED: marlin only 17,663->17,463us/step (-200us) — the count was cheap because the
+fused 2N GEMM reads the SAME weight bytes as 2 narrow ones (W4A16 memory-bound). So step 2 is
+STRUCTURAL/correctness parity, not a speed win; its value is ISOLATING the residual cleanly.
+
+STEP 3 — CTA-COUNT root-cause + par=1 arbiter (opt-in, DEFAULT OFF). ROOT: `blocks = sms *
+exec_cfg.blocks_per_sm` (marlin_mm_moe.cu:494); for E=1 decode `determine_exec_config` picks
+par=3 => 48*3 = **144 CTAs** (persistent grid) vs vLLM dense marlin's tile-per-CTA **48**
+(GB10 sms=48). Post-step-2 FAIR residual (both graphed, M=8): at matched 144-count ours marlin
+121.3us/call vs vLLM 113.1 = **+7.2%/call = +1,177us/step = the DOMINANT residual** (REFUTES
+#52's "per-call near-parity, memory-bound" — the CTA count IS the cost, not the GEMM count).
+ARBITER (VT_MARLIN_E1_PAR1, same-tool in-model c8 window): clamp par=1 (blocks==sms==48) drops
+marlin 17,463->16,512us/step (-5.4%, per-call 114.7 => +1.4% NEAR-PARITY) and TPOT 37.22->36.23ms,
+TOKEN-EXACT on 8B-MXFP4 (#44 smoke 3/3). => the launcher fix is MEASURABLY SUFFICIENT (recovers
+81% of the marlin residual) WITHOUT the ~2000-line dense-template port (#50 NO-GO). BUT default
+BLOCKED: on 64-layer Qwen3-32B-NVFP4A16 the par=1 fp32-reduce regroup accumulates a 1-ULP flip
+into a STRICT token divergence vs the committed anchor (`REQUIRE` at :344; ISOLATED: baseline
+142/142, graph-only 142/142, par1-only 59/60 FATAL). Real MoE (num_experts>1: 27B/35B/Coder)
+UNTOUCHED by construction; prefill (thread_m_blocks>1) untouched. Shipped opt-in; a byte-
+PRESERVING CTA reduction = the dense-template marlin port (scoped, next dispatch).
+
+STEP 4 — same-tool residual map (nsys `--cuda-graph-trace=node` c8, M=8-pinned, 235 steady steps;
+vLLM side reused from #52, same pin). ours-default(graph+fuse) vs ours+par1 vs vLLM, us/step:
+| class | ours-dflt(144) | ours+par1 | vLLM(144) | dflt gap | par1 gap |
+| marlin | 17,463 | 16,512 | 16,286 | +1,177 | +226 |
+| flash  |  6,413 |  6,436 |  5,629 | +784   | +807  |
+| glue   |    866 |    869 |    671 | +195   | +198  |
+| SPAN   | 30,732 | 29,800 | 28,491 | +2,241 | +1,309 |
+| TPOT ms|  37.22 |  36.23 |  34.58 | +2.64  | +1.65 |
+VERDICT: shipping default (graph+fuse, par1 OFF) banks the graph gain + GEMM-count structural
+parity (144==144); the c8 residual is marlin CTA (+1,177, 53%, closable to +226 near-parity via
+par1/dense-port), flash (+784, 35%, SAME kernel+grid — KV-read/splitkv-scratch, unresolved), glue
+(+195, 9%, portable-fusion). With par1 opt-in FLASH becomes the dominant residual. The full strict
+binding ratio table (c1..c8 x3, fresh oracle) is DEFERRED: the strict-record harness needs an
+on-REAL-disk RelWithDebInfo build (tmpfs fails the mincore cache-drop proof) + the vLLM oracle,
+whose host-RAM reservation alongside the 27G tmpfs tree is the GB10 OOM-reboot risk — not run.
+
+Gates on GB10 (5 rebuilds, EXIT=0 each): unit `test_linear_method` 7/7·56; `test_qwen3_paged_engine`
+184/184 (graph ON==OFF, and at flipped default); `test_qwen3_dense_async_serving` 82/82; #44
+MXFP4-8B smoke 3/3 token-exact (fused==split, graph on/off, par1 on/off); `test_qwen3_32b_nvfp4a16_
+paged_engine` 142/142 at the pure shipping default. Evidence dgx:~/mxfp4-nsys/{oursfused_c8,ourspar1_c8}
+.nsys-rep + kern_sum_oursfused_c8.txt + gpu_trace_oursfused_c8_*.csv, ~/{gate2,gate4,gate5,iso32b,
+step1_gate,step1_smoke}.log. Env: `VLLM_CPP_QWEN3_DENSE_DECODE_GRAPH` (now default ON), `VT_MOE_FUSED_W13`
+(default ON, now covers mxfp4), `VT_MARLIN_E1_PAR1` (NEW, default OFF opt-in).
diff --git a/docs/BENCHMARKS.md b/docs/BENCHMARKS.md
@@ -307,7 +307,7 @@ built on it rather than keeping the flattering one.
 | Qwen3-dense decode CUDA-graph | Token-exact pass, ~4.3% e2e directional | Steady-state per-step tok/s |
 | Kimi-Linear-48B-A3B (KDA+MLA+MoE) | Full-model GB10 e2e RUNS (bf16-resident §13), NEAR-TIE 106/128, pool math CLOSES; default OFF | Full model RUNS on GB10 (bf16-resident, RSS peak 1.7 GiB, min-avail 21 GiB, no OOM). Token NEAR-TIE 106/128 (6/8 prompts exact, numerics vs deterministic oracle). 1.59 tok/s. Detail: spec §13 |
 | vLLM 0.26 re-benchmark | Pending | Re-run the binding grids on the advanced pin |
-| MXFP4 Qwen3-8B (W4A16 Marlin) | Closers binding x3 (d3b412f5): c1 **1.005 PASSES**, c2/c4/c8 0.925/0.939/0.953 BELOW (+0.3/0.9/1.1pp vs #49), TTFT parity, mem 2.18x WIN; byte-exact slivers (bitdiff=0), #44 3/3, gate NO | c8 same-tool diff (`QUANT-CT-MXFP4-C8-DIFF`): marlin grouped-5-GEMM DOMINANT (gate_up unfused); eager gap +0.88ms graph-closeable (decode-graph opt-in +1.3%); flash same-grid +11%; #50 = isolated-shape artifact |
+| MXFP4 Qwen3-8B (W4A16 Marlin) | #51 x3: c1 1.005, c2/c4/c8 0.925/0.939/0.953, mem 2.18x. `MARLIN-STRUCT`: decode-graph + gate_up FUSION default-ON, marlin 180->144 GEMM/step (vLLM-structural); #44 3/3, 32B-NVFP4A16 142/142 | nsys c8 residual: marlin +1,177us (CTA 144 vs 48, dominant), flash +784, glue +195. `VT_MARLIN_E1_PAR1` opt-in (E=1 grid to 48 CTAs) near-parity but flips a strict 32B token (default-OFF). Detail in benchmark-record |
 | SGLang floor arms | Never ran | Both arms of the SGLang comparison |
 | cuBLAS invocation-parity guard | CI guard landed (CPU); `kGemvHeuristicAlgos` refactor build-verify owed | `nvcc` rebuild + SACRED gate on dgx |
 

diff --git a/docs/ENVIRONMENT.md b/docs/ENVIRONMENT.md
@@ -56,7 +56,9 @@ portable/reference path. In normal operation leave them unset.
 | `VT_ASYNC_EXECUTOR` | off (opt-in) | `=1` enables Option A: the decode-graph per-step input H2D staged OUT of the captured replay (the c16/c32 overlap unlock, ENG-ASYNC-SCHED). The Qwen3.5 MoE/dense decode-graph drivers give each padded-size slot PERSISTENT device input buffers the captured graph reads and PINNED host staging; per step the input H2D is enqueued on the main queue BEFORE `ReplayGraph` and an input-staged event is recorded right after it, so the next same-slot Refresh waits only that tiny copy, never the GPU tail (the faithful vLLM `_prepare_input_ids`/`synchronize_input_prep` structure, `states.py:64`). The 2-slot parity ring is retained (the depth-2 loop enqueues sample(i-1) after forward(i), so persistent logits must double-buffer). The runner skips the depth-2 pre-forward `Synchronize` whenever the previous step's logits are a non-owning graph-slot view. Default OFF routes through the single-slot baked-H2D driver with the drain intact — byte-identical to production. No effect on CPU or the sync `LLMEngine`. `=1` roughly doubles the captured decode-graph memory (logits-dominated) and adds small pinned host + persistent device input buffers per slot |
 | `VLLM_CPP_CUDAGRAPH` | on (CUDA) | Eager launches instead of a captured CUDA graph |
 | `VLLM_CPP_DENSE_DECODE_GRAPH` | on (CUDA dense) | Non-graphed dense decode |
-| `VLLM_CPP_QWEN3_DENSE_DECODE_GRAPH` | off (opt-in) | `=1` routes pure-decode steps for the SHARED pure-dense forward (`Qwen3DenseModel`, i.e. Qwen3 / Llama / InternLM3 / Mistral / InternLM2 `ForCausalLM`) through the captured decode CUDA graph; default OFF keeps the byte-identical eager decode. Token-exact with eager (dgx SACRED near-tie gate, Qwen3-0.6B/4B). Honors `VLLM_CPP_CUDAGRAPH=0` |
+| `VLLM_CPP_QWEN3_DENSE_DECODE_GRAPH` | **on** | Routes pure-decode steps for the SHARED pure-dense forward (`Qwen3DenseModel`, i.e. Qwen3 / Llama / InternLM3 / Mistral / InternLM2 `ForCausalLM`) through the captured decode CUDA graph. **DEFAULT-ON since `QUANT-CT-MXFP4-MARLIN-STRUCT`** (parity-enabler; banks ~+1.3% TPOT@c8 by collapsing the eager inter-kernel launch gap). Token-exact with eager — `=0` opts out to the byte-identical eager decode; gated dgx SACRED `test_qwen3_paged_engine` 184/184 (graph ON==OFF, Qwen3-0.6B near-tie + 4B), async 82/82, Qwen3-8B-MXFP4 #44 smoke 3/3, Qwen3-32B-NVFP4A16 142/142. Honors `VLLM_CPP_CUDAGRAPH=0` |
+| `VT_MOE_FUSED_W13` | on | Runs a dense/shared MLP gate+up PAIR as ONE Marlin GEMM over the N-concatenated `[2I,H]` operand + `SiluAndMul` (vLLM's merged `gate_up_proj` structure), instead of two split GEMMs + `MoeSiluMul`. **Generalized NVFP4→MXFP4 in `QUANT-CT-MXFP4-MARLIN-STRUCT`** (drops the classic-dense Qwen3-8B-MXFP4 decode from 180→144 marlin GEMM/step = vLLM-structural parity). `=0` is the split A/B fallback. Numerically equivalent to split (the fused fp32 split-K reduce regroups by 1 bf16 ULP; token-exact vs the oracle — #44 fused==split 3/3, unit `test_linear_method` 99.9% bit-exact) |
+| `VT_MARLIN_E1_PAR1` | off (opt-in) | `=1` clamps the single-expert (`num_experts==1`) DECODE marlin grid to `sms×1` (48 CTAs on GB10) instead of the persistent `sms×par` grid `determine_exec_config` auto-picks (par=3 → 144 CTAs), matching vLLM's dense marlin tile-per-CTA count. Measured same-tool in-model (Qwen3-8B-MXFP4 c8): marlin 17,463→16,512 us/step (−5.4%, per-call 121.3→114.7 vs vLLM 113.1 = near-parity), TPOT 37.22→36.23 ms, token-exact on 8B-MXFP4. **DEFAULT OFF**: `par` regroups the fp32 C_tmp reduce, so the E=1 output differs by 1 bf16 ULP — on the 64-layer Qwen3-32B-NVFP4A16 that accumulates into a strict-token flip vs its committed SACRED anchor (`test_qwen3_32b_nvfp4a16_paged_engine` REQUIRE :344). Real MoE (`num_experts>1`) and prefill (`thread_m_blocks>1`) are untouched (byte-identical) |
 | `VT_MM_DECODE_EAGER` | off (graph on) | Set to `1` to force the eager per-step multimodal (Qwen3.6-27B image/video) decode instead of routing it through the captured dense decode graph. Rollback / A-B knob; the graphed path is token-exact with the eager path |
 | `VT_KIMI_DEVICE_COMPUTE` | off (opt-in) | `=1` routes the Kimi-Linear-48B-A3B runner path (`KimiLinearModel::ForwardDevice`) through the W7 DBuf-resident device COMPUTE (`ForwardDeviceCompute`, the whole KDA/NoPE-MLA + MoE hybrid over pooled DBufs via the shared vt:: ops) instead of the default W6 host-reference compose. Default OFF keeps the CPU-verified host-ref-compose seam as production until the device compute is GPU-verified against the SACRED oracle; the device compute is CPU-gated (`test_kimi_linear_forward`, device==W2 reference within f32-accumulation tolerance, greedy-token-identical) but its GPU numerics are a NAMED pending. The flag exists so the device path CAN be exercised as the runner path for that verification |
 | `VT_WHISPER_ENC_EAGER` | off (flash-tiled attention on) | Set to `1` to force the naive per-key block-reduction attention in the Voxtral/Whisper audio encoder instead of the default flash-tiled kernel. Rollback / A-B knob; token-identical to the default path |

diff --git a/docs/FEATURES.md b/docs/FEATURES.md
@@ -65,7 +65,7 @@ are our reading of their documented behavior, not measurements.
 | GGUF k-quants and i-quants | ✅ | ☐ | ☐ | ✅ |
 | AWQ | ◐ CPU dequant | ✅ | ✅ | ☐ |
 | GPTQ | ◐ CPU dequant | ✅ | ✅ | ☐ |
-| MXFP4 compressed-tensors | ◐ W4A16 Marlin compute proven; e2e 3/4 token-exact; mem 2.6x less. FA2 GQA group-swap **DEFAULT-ON**: binding tput c2-c8 →0.922/0.930/0.942 (c1 flat, no reg); SACRED 0.6B/4B token-identical; still <1.0x | ✅ | ✅ | ☐ |
+| MXFP4 compressed-tensors | ◐ W4A16 Marlin compute proven; mem 2.6x less. gate_up FUSION + decode-graph default-ON (marlin 180->144 GEMM/step, vLLM-structural); #44 3/3, 32B 142/142. Residual = marlin CTA (`VT_MARLIN_E1_PAR1` opt-in), <1.0x | ✅ | ✅ | ☐ |
 | fp8 weights | ✅ | ✅ | ✅ | ☐ |
 | bf16 / fp16 | ✅ | ✅ | ✅ | ✅ |
 | Safetensors direct load, no conversion | ✅ | ✅ | ✅ | ☐ |