row/H3-DIT-SCALE-GATE: DiT spatial-mixing geometry ladder (#70 close)

.agents/NOW.md

@@ -18,7 +18,7 @@ checkpoint on `upstream/main` at `59674cf1d`.
 | DeepSeek-V4-Flash decode | **Closed: beats ds4 1.144x** (`VT_V4_RESIDENT_W`, byte-exact); phase-2 residency NEG, default-OFF | — |
 | f32-out GEMV audit | Only laguna + ds4 bf16 tower affected; gate models unaffected | Re-verify ds4 tower same-tool |
 | Invocation-parity prevention | CI guard + AGENTS.md checklist landing | Merge; build-verify `kGemvHeuristicAlgos` on dgx |
-| MiniMax-H3 lane | **Render bug ROOT-CAUSED** (#70): VAE FINE, **DiT latent spatially WHITE** (0.06 vs 0.79) | Pin DiT line; fp4 CLOSED |
+| MiniMax-H3 lane | **#70** DiT-math bug REFUTED (`H3-DIT-SCALE-GATE` PR #74): ladder 2x3->8x8+temporal ours==oracle host+dev <=3e-7; white=TRAINED | dgx: real upstream vs RefDiT |
 | Kimi-Linear-48B (KDA+NoPE-MLA+MoE) | **e2e RUNS** (bf16-resident §13): 13/13·656. Token gate **NEAR-TIE 106/128** | device GDN/MLA islands; 1.59 tok/s; default OFF |
 | 35B fresh grid | **BOUND** @`1ea26427`: 0.93-1.03x, c16 0.93x. INTAKE + Option A both NEGATIVE | Lever left: prefill glue (#61) |
 | Qwen3.5-4B revalidation | 0.9971x @`59674cf1` (#35); TTFT/PSS pass, TPOT/ITL open | `docs/bench-evidence/` |

.agents/benchmark-record.md

@@ -14044,3 +14044,78 @@ DiT-activation diff at real geometry — impractical on one GB10 (no quantized
 vllm-omni H3 arm; bf16 is 4xB300). Diagnostics committed on PR #70; latents at
 `dgx:~/h3fp4/diag`. fp4 speed path unchanged/CLOSED. No source/kernel/model/gate
 mark changed (all additions are env-gated diagnostics, byte-identical when off).
+
+## MiniMax-H3 DiT-forward GEOMETRY LADDER — the #70 spatial-mixing hypothesis is REFUTED at reduced dims; the divergence is NOT a reduced-dim-reproducible DiT math bug (2026-08-06, `row/H3-DIT-SCALE-GATE` PR #74, `ROAD-V1-H3`, CPU-only dev box)
+
+**Question (#70 follow-up).** #70 root-caused the H3 render grid to the DiT emitting
+a spatially-WHITE latent at real token geometry (adjacent-cell cosine 0.06 vs 0.789
+for a real encode; VAE/loop/fp4/bf16/attention-kernels all ruled out). The DiT parity
+gate only ran 2x3 spatial tokens (1.6e-7 vs upstream). Hypothesis: a spatial-MIXING
+bug in position/packing/modulation MATH (not weight values) should reproduce with the
+H3Rand random-weight harness at real TOKEN geometry with reduced hidden dims.
+
+**Method (CPU-only, no dgx).** Extended the reduced-dim DiT-forward parity gate
+(`scripts/gen-minimax-h3-goldens.py` :: `emit_dit_ladder`; RefDiT oracle + upstream
+`minimax_h3_packed_sequence`, both from the shared FNV-1a+splitmix64 stream) into a
+GEOMETRY LADDER. Each rung gates, at reduced hidden dims (hidden=64, head_dim=16):
+(1) the upstream packed-sequence layout (cu_seqlens / img_position_ids fp64 grid /
+masks — the 2x3-only packed gate was the same blind spot); (2) the HOST forward
+(`MiniMaxH3DitForward`); (3) the DEVICE-resident forward (`MiniMaxH3DitForwardDevice`,
+CPU backend — the path the real pipeline runs); (4) a spatial-MIXING probe (perturb one
+video-target token, measure the per-output response). New permanent gate case
+`test_minimax_h3.cpp :: "DiT-forward geometry ladder matches upstream (host+device,
+mixing)"`. Goldens regenerate byte-identically against local `~/_git/vllm-omni`.
+
+**Ladder result — ours == upstream oracle at EVERY rung (host AND device):**
+| Rung | latent t×h×w | spatial grid | video tokens | host max\|diff\| | device max\|diff\| | mix fraction | verdict |
+|---|---|---|---|---|---|---|---|
+| 2x3 | 1×4×6 | 2×3 | 12 (6 tgt) | 1.8e-7 | ≤2.4e-7 | 1.0 | PASS |
+| 4x4 | 1×8×8 | 4×4 | 32 (16 tgt) | 1.8e-7 | ≤2.4e-7 | 1.0 | PASS |
+| 6x6 | 1×12×12 | 6×6 | 72 (36 tgt) | 2.1e-7 | ≤2.4e-7 | 1.0 | PASS |
+| **8x8** | 1×16×16 | **8×8** | **128 (64 tgt)** | **2.4e-7** | **≤2.4e-7** | **1.0** | **PASS** |
+| 4x8 | 1×8×16 | 4×8 | 64 (32 tgt) | 1.8e-7 | ≤2.4e-7 | 1.0 | PASS |
+| 8x8t3 | 3×16×16 | 8×8 ×3f | 256 (192 tgt) | 2.4e-7 | ≤2.4e-7 | 1.0 | PASS |
+| 12x20t5 | 5×12×20 | 6×10 ×5f | 360 (300 tgt) | 3.0e-7 | ≤5.4e-7 | 1.0 | PASS |
+
+All ≤ 3e-7 vs the 2e-5 gate. The mixing probe: perturbing ONE video-target token
+changes EVERY other target token's output (fraction 1.0 at all rungs) — the packed
+bidirectional attention (`cu_seqlens = [0, used, seq_len]`, one document) couples all
+video tokens at real geometry, exactly the property #70 found broken in the real run.
+
+**Hidden-dim-scale leg (the other #70 escape hatch).** A second gate case runs the SAME
+geometries at the REAL head_dim=128 / rope_inv_freq_len=16 (rot_dim=96) ratio and
+requires the DEVICE forward to track the trusted HOST loops (no oracle needed).
+Device-vs-host max\|diff\| = 5e-7…1.2e-6 across all 7 rungs — no head_dim- or
+rope-scale assumption in a shared device op. `"DiT device-vs-host forward holds at the
+REAL head_dim=128 ratio"`.
+
+**The metric that does NOT translate (why the ladder can't SHOW #70's symptom).**
+Measured the #70 adjacent-cell COSINE on the CORRECT RefDiT oracle output at reduced
+dims: adj_cos ≈ random-pair cos ≈ 0 at EVERY geometry (2x3 +0.11/−0.03; 8x8
++0.05/−0.01; 8x8t3 +0.02/+0.02). With RANDOM weights the correct reference is ALREADY
+spatially white by the cosine metric — spatial coherence in the real model is a
+TRAINED-WEIGHTS property, not an architecture-math property. So the random-weight
+harness fundamentally cannot reproduce #70's cosine symptom; its valid discriminators
+are oracle-logit equality and information flow (both green), NOT the cosine.
+
+**VERDICT.** The "spatial-mixing bug in the DiT-forward MATH" hypothesis is **REFUTED**
+at reduced dims and real token geometry: our port (host AND device) is byte-exact to the
+oracle at 2x3→8x8→temporal→packed-mix and at the real head_dim=128 ratio, and the
+attention demonstrably mixes all video tokens. The #70 white latent is therefore NOT a
+reduced-dim-reproducible DiT-forward bug; it is a **trained-weights / real-scale**
+phenomenon the harness cannot see. A **GPU re-render is NOT expected to be coherent** on
+the strength of this work — nothing was fixed in the render path; the secondary Gaussian-
+noise fix from #70 stands but was already known not to be the render fix.
+
+**Residuals / where the #70 hunt goes next (both beyond this CPU box):**
+1. **Shared port⇄RefDiT bug vs TRUE upstream.** `vllm`/`cache_dit`/`aenum` are not
+   importable here, so the DiT oracle is the RefDiT *restatement*, not the real
+   `minimax_h3_transformer.py`. A bug shared identically by our port AND RefDiT (a
+   co-mirrored misreading) is invisible to this ladder ("gate on a shared helper =
+   consistency, not correctness"). CLOSE IT on the dgx oracle venv (vllm IS installed):
+   run the real `MiniMaxH3DiTModel` at TP=1 / reduced dims vs RefDiT.
+2. **Real-scale DiT INPUT wiring.** The harness feeds RANDOM prompt-embeds / video rows;
+   the real render feeds the Qwen3-VL encoder embeddings, the real fp64 position grid at
+   full canvas, and the real per-token timestep layout. A real-weights activation diff of
+   the DiT INPUTS (encoder output, position grid, condition-noise) at real geometry is
+   the untested surface #70 did not isolate.

.agents/specs/minimax-h3.md

@@ -488,3 +488,41 @@ video flow_shift 12 / audio 3, no CFG; default canvas **768×1344**, default fra
   GPUs + BF16 + USP-4 + torch.compile + block-caching vs one GB10 + fp4 + none, and
   vLLM-Omni cannot serve a quantized H3 on one GPU at all. The honest same-box number
   is the fp4-vs-bf16 ratio (0.79–0.83× per forward, 4× less weight memory).
+### 8.5 DiT-forward GEOMETRY LADDER — the #70 spatial-mixing hypothesis REFUTED (2026-08-06, `row/H3-DIT-SCALE-GATE` PR #74, CPU-only)
+
+The §8.4 render bug (#70) was root-caused to the DiT emitting a spatially-WHITE latent
+at real token geometry, with the DiT parity gate only ever run at spatial 2×3. This row
+tested the leading hypothesis — a spatial-MIXING bug in the position/packing/modulation
+MATH, reproducible with random weights at real TOKEN geometry — by extending the
+reduced-dim DiT gate into a GEOMETRY LADDER.
+
+- **Built:** `emit_dit_ladder` in `scripts/gen-minimax-h3-goldens.py` (7 rungs: 2×3, 4×4,
+  6×6, **8×8**, a 4×8 rectangle, an 8×8×3-frame temporal 3D grid, and a 6×10×5-frame
+  video+audio packed mix), and the permanent gate case `test_minimax_h3.cpp :: "DiT-forward
+  geometry ladder matches upstream (host+device, mixing)"`. Each rung gates the upstream
+  packed-sequence layout (cu_seqlens / fp64 position grid / masks), the HOST forward, the
+  DEVICE-resident forward (the pipeline's own path), and a spatial-MIXING probe.
+- **Result: ours == the RefDiT oracle at EVERY rung**, host AND device, max|diff| ≤ 3e-7
+  vs the 2e-5 gate. The mixing probe: perturbing one video-target token changes EVERY
+  other target token (fraction 1.0 at all rungs) — the packed bidirectional attention
+  (`cu_seqlens=[0,used,seq_len]`, one document) couples all video tokens at real geometry.
+- **Hidden-dim-scale leg:** a second case reruns the geometries at the REAL head_dim=128 /
+  rope_inv_freq_len=16 (rot_dim=96) ratio and requires the DEVICE forward to track the
+  trusted HOST loops — device-vs-host ≤ 1.2e-6 across all rungs (no head_dim/rope-scale
+  device-op assumption).
+- **Why the ladder cannot SHOW #70's symptom:** measured the #70 adjacent-cell COSINE on
+  the CORRECT oracle at reduced dims — adj_cos ≈ random-pair ≈ 0 at every geometry. With
+  RANDOM weights the correct reference is ALREADY white by the cosine metric; spatial
+  coherence is a TRAINED-WEIGHTS property. The harness's valid discriminators are oracle-
+  logit equality and information flow (both green), not the cosine.
+- **VERDICT:** the "spatial-mixing bug in the DiT-forward MATH" hypothesis is **REFUTED**.
+  The #70 white latent is NOT a reduced-dim-reproducible DiT-forward bug — it is a
+  trained-weights / real-scale phenomenon. A GPU re-render is NOT expected to be coherent
+  from this work; nothing in the render path was changed.
+- **Residuals (both beyond the CPU box):** (1) a bug shared identically by our port AND the
+  RefDiT restatement vs TRUE upstream `minimax_h3_transformer.py` (not importable here —
+  no `vllm`/`cache_dit`/`aenum`) is invisible to this ladder; close it on the dgx oracle
+  venv where vllm is installed. (2) the real-scale DiT INPUT wiring (Qwen3-VL encoder
+  embeddings, real fp64 position grid at full canvas, real per-token timesteps) is fed with
+  RANDOM data here; a real-weights activation diff of the DiT inputs is the untested surface.
+  Full tables: benchmark record (`row/H3-DIT-SCALE-GATE`).

.agents/state.md

@@ -39537,3 +39537,67 @@ are committed on the row for the next session. fp4 speed path stays CLOSED.
 Box left clean (GPU idle, both locks free, worker down, ~39 G ckpt cached at
 `dgx:~/h3fp4/ckpt`, diagnostic latents at `dgx:~/h3fp4/diag`). Evidence:
 `dgx:~/h3fp4/{diag,rt_out,out_small,out_cond}`; PR #70.
+## 2026-08-06T20:45 - H3 DiT geometry-ladder gate CLAIMED (row/H3-DIT-SCALE-GATE, helper, DRAFT PR) - pin the #70 spatial-mixing divergence at real token geometry
+<!-- state: 2026-08-06T20:45 -->
+
+`row/H3-DIT-SCALE-GATE` (helper, isolated worktree off `origin/main` f7a1e322,
+DRAFT PR). CPU-ONLY (no dgx). Follow-up to #70, which root-caused the H3 render
+grid to the DiT emitting a spatially-WHITE latent at real token geometry (VAE,
+denoise loop, fp4/bf16 residency, attention kernels all ruled out). The
+reduced-dim DiT parity gate only ever ran 2x3 spatial tokens (1.6e-7 vs
+upstream); the divergence appears between 2x3 and the real 8x8 grid.
+
+PLAN: extend `scripts/gen-minimax-h3-goldens.py` `emit_dit` into a GEOMETRY
+LADDER (2x3 -> 4x4 -> 6x6 -> 8x8 + rectangle + multi-frame temporal + video+audio
+packed mix) at reduced hidden dims, running the same RefDiT oracle + upstream
+`minimax_h3_packed_sequence`; gate BOTH the host forward (`MiniMaxH3DitForward`)
+AND the device-resident forward (`MiniMaxH3DitForwardDevice`, CPU backend, the
+one the real pipeline uses) against it at every rung. Find the FIRST rung where
+ours diverges; bisect per-op; fix (mirror upstream); keep 63/63 green; add the
+ladder as a permanent below-one-tile gate. If the ladder does NOT reproduce even
+at 8x8+temporal+mix, record that verdict with data and redirect to the
+device-vs-host diff at ladder geometry. Harness verified: gen script reproduces
+the checked-in goldens byte-identically against the local `~/_git/vllm-omni`.
+## 2026-08-06T20:55 - H3 DiT geometry-ladder BUILT + run: #70 spatial-mixing-math hypothesis REFUTED; the white latent is trained-weights/real-scale, not a reduced-dim DiT bug
+<!-- state: 2026-08-06T20:55 -->
+
+`row/H3-DIT-SCALE-GATE` (helper, DRAFT PR #74, CPU-only). Extended the reduced-dim
+DiT-forward parity gate into a GEOMETRY LADDER (`emit_dit_ladder` in
+`scripts/gen-minimax-h3-goldens.py`; 7 rungs 2x3->4x4->6x6->8x8 + 4x8 rectangle +
+8x8x3-frame temporal + 6x10x5-frame video+audio packed mix) and added two permanent
+gate cases in `test_minimax_h3.cpp`. Goldens regenerate byte-identically vs local
+`~/_git/vllm-omni`. Full suite 65/65 (was 63/63).
+
+**Result — ours == the RefDiT oracle at EVERY rung, HOST and DEVICE forward,
+max|diff| <= 3e-7 vs the 2e-5 gate.** The spatial-mixing probe (perturb one
+video-target token) shows fraction 1.0 at all rungs: the packed bidirectional
+attention (`cu_seqlens=[0,used,seq_len]`, one document) couples all video tokens at
+real geometry — exactly the property #70 found broken in the real run. A second case
+reruns the geometries at the REAL head_dim=128 / rope_inv_freq_len=16 ratio and
+requires DEVICE==HOST (<= 1.2e-6 across all rungs): no head_dim/rope-scale device-op
+assumption either.
+
+**The metric that does not translate:** measured the #70 adjacent-cell COSINE on the
+CORRECT oracle output — adj_cos ~= random-pair ~= 0 at every geometry (even 2x3). With
+RANDOM weights the correct reference is ALREADY white by the cosine metric; spatial
+coherence is a TRAINED-WEIGHTS property, so the random-weight harness fundamentally
+cannot reproduce #70's cosine symptom. The ladder's valid discriminators are
+oracle-logit equality and information flow, both green.
+
+**VERDICT:** the "spatial-mixing bug in the DiT-forward MATH" hypothesis is REFUTED at
+reduced dims and real token geometry. The #70 white latent is NOT a reduced-dim-
+reproducible DiT-forward bug; it is trained-weights / real-scale. A GPU re-render is
+NOT expected to be coherent from this work (nothing in the render path changed). The
+mission's fallback (diff DEVICE vs HOST at ladder geometry) is DONE here: both match
+the oracle at every rung, so the device path is not the culprit at real token geometry.
+
+**Residuals / handoff (both beyond this CPU box):** (1) a bug shared identically by our
+port AND the RefDiT restatement vs TRUE upstream `minimax_h3_transformer.py` (not
+importable here: no vllm/cache_dit/aenum) is INVISIBLE to this ladder ("gate on a
+shared helper = consistency, not correctness"). Close it on the dgx oracle venv (vllm
+installed): run the real MiniMaxH3DiTModel at TP=1 / reduced dims vs RefDiT. (2) the
+real-scale DiT INPUT wiring (Qwen3-VL encoder embeddings, real fp64 position grid at
+full canvas, real per-token timesteps) is fed with RANDOM data in the harness; a
+real-weights activation diff of the DiT inputs at real geometry is the untested
+surface #70 did not isolate. Pre-existing preflight red
+(check-fusion-consistency minimax_h3_video_vae_device) is NOT this row's.

docs/BENCHMARKS.md

@@ -302,7 +302,7 @@ built on it rather than keeping the flattering one.
 | Qwen3-dense decode CUDA-graph | Token-exact pass, ~4.3% e2e directional | Steady-state per-step tok/s |
 | Kimi-Linear-48B-A3B (KDA+MLA+MoE) | Full-model GB10 e2e RUNS (bf16-resident §13), NEAR-TIE 106/128, pool math CLOSES; default OFF | Full model RUNS on GB10 (bf16-resident, RSS peak 1.7 GiB, min-avail 21 GiB, no OOM). Token NEAR-TIE 106/128 (6/8 prompts exact, numerics vs deterministic oracle). 1.59 tok/s. Detail: spec §13 |
 | vLLM 0.26 re-benchmark | Pending | Re-run the binding grids on the advanced pin |
-| MiniMax-H3 FP4 speed (W-FP4a) | **Measured GB10 (`row/H3-FP4-GPU-E2E`).** Marlin W4A16 byte-exact vs bf16; fp4 a memory win, 0.8x bf16/forward. Real-ckpt fp4-resident e2e RUNS (mp4/wav) but frame is a non-scene patch-grid | Render coherence ROOT-CAUSED (#70): VAE fine, DiT latent spatially white. fp4 speed CLOSED. Detail: benchmark-record + spec §8 |
+| MiniMax-H3 FP4 speed (W-FP4a) | **Measured GB10 (`row/H3-FP4-GPU-E2E`).** Marlin W4A16 byte-exact vs bf16; fp4 a memory win, 0.8x bf16/forward. Real-ckpt fp4-resident e2e RUNS (mp4/wav) but frame is a non-scene patch-grid | Render coherence ROOT-CAUSED (#70): VAE fine, DiT latent white. Geometry ladder (PR #74) REFUTES a DiT-math bug: ours==oracle to 8x8+temporal; white=trained-wts. fp4 speed CLOSED. Detail: benchmark-record + spec §8 |
 | MXFP4 Qwen3-8B (W4A16 Marlin) | **`KERNEL-MARLIN-DENSE-EXEC` x3 (dense-ON default): c1 1.020, c2/c4/c8 0.962/0.966/0.969, GPU mem 2.63x less** (beats #51 1.005/0.925/0.939/0.953 EVERY axis); #44 3/3, 32B-NVFP4A16 6/6; -Werror test-guard fixes x2 | **VT_MARLIN_DENSE default-ON** banks +951us marlin. `FUSED-GLUE` W0: glue-into-marlin REFUTED (vLLM doesn't fuse into extern marlin); `FLASH-AUDIT` #68: c8 flash occupancy/L2-bound; `-use_fast_math` regresses, rejected |
 | SGLang floor arms | Never ran | Both arms of the SGLang comparison |
 | cuBLAS invocation-parity guard | CI guard landed (CPU); `kGemvHeuristicAlgos` refactor build-verify owed | `nvcc` rebuild + SACRED gate on dgx |

docs/FEATURES.md

@@ -131,7 +131,7 @@ they sit outside the gated list above.
 |---|---|---|---|
 | Voxtral audio (`VoxtralForConditionalGeneration`) | Voxtral-Mini-3B-2507 | near-tie-robust 16/16 vs vLLM 0.25.0 | decode 0.97x (beats vLLM); encoder TTFT ~17x, pending |
 | Whisper audio encoder | openai/whisper-small; whisper-large-v3 (Voxtral cfg) | encoder tower 77/77; large-v3 tower 203/203 | pending |
-| MiniMax-H3 DiT (`MiniMaxH3DiTModel`, vllm-omni lane) | MiniMax-H3 (33.1B video+audio) | portable path 62/62; real-weights render coherence OPEN | FP4/Marlin routing landed, GB10 speed pending |
+| MiniMax-H3 DiT (`MiniMaxH3DiTModel`, vllm-omni lane) | MiniMax-H3 (33.1B video+audio) | portable path 65/65 (DiT geometry ladder 2x3->8x8+temporal, host+device vs oracle); real-weights render coherence OPEN (DiT-math bug REFUTED by the ladder, PR #74) | FP4/Marlin routing landed, GB10 speed pending |
 | MTP speculator | Qwen3.6-27B, Qwen3.6-35B-A3B | token-identical to vLLM `mtp` at c1 | ~4% faster c1; +16% output tput (MoE) |
 | DFlash block-diffusion | Qwen3 (DFlash draft) | near-tie e2e 27/27 vs vLLM | 2.9x over spec-off, 1.003x vs vLLM DFlash-on |
 | DeepSeek-V4 MTP | DeepSeek-V4-Flash (nextn head) | lossless 5/5; real-model weight-blocked | pending |