Here is the detailed README.md file for the new repository, inspired by the EBAZ4205-AtariTetris context.
Repository Name: EBAZ4205-OrbitalDefender
Core Concept: Re-imagining the classic "Space Defender" arcade genre as a pure, synthesized hardware core on the EBAZ4205 ZYNQ-7010 FPGA board. This is not an emulation; it is a logic-level reconstruction of a hypothetical 1982 raster-to-vector hybrid arcade machine.
This project bridges the gap between bespoke hardware design and retro gaming. Where EBAZ4205-AtariTetris focused on the iconic tile-matching puzzle, OrbitalDefender tackles high-speed vector rasterization, parallax starfields, and a custom sprite pipeline—all running on the affordable EBAZ4205 board.
Imagine a game that doesn't just "run" on an FPGA but becomes the FPGA. The logic gates are the enemy ships. The LUTs generate the explosion particles. This repository is a blueprint not just for a game, but for a hardware-defined experience. It respects the limitations of the ZYNQ-7010 (a mere 28k Logic Cells) by treating them not as a constraint, but as a design philosophy.
- Hardware-Accelerated Vector Rendering: We utilize the PL (Programmable Logic) to draw continuous vectors, emulating the look of a Vectrex-style display, but outputting to a standard HDMI monitor.
- PS/PL Hybrid Architecture: The ARM Cortex-A9 (Processing System) handles game state, AI routines, and sound mixing, while the FPGA fabric handles every single pixel and collision detection.
- Open Source Silicon Canvas: Every Verilog module is designed for readability and modification, allowing you to "rewire" the game logic.
Before diving into the hardware jungle, secure the core files.
- Download the Bitstream & Boot Files: This includes the
BOOT.BIN,devicetree.dtb, and the synthesized.bitfile. - Download the Vivado Project Source (RTL): For those who wish to synthesize from scratch.
The following diagram illustrates the data flow from the PS (Processing System) to the PL (Programmable Logic) and out to the display.
graph LR
subgraph "ZYNQ-7010 PS (ARM Cortex-A9)"
A[Game Engine (C)] --> B{Videocore Frame Buffer}
B --> C[AXI4-Lite Control Bus]
A --> D[Sound Mixer (I2S)]
end
subgraph "ZYNQ-7010 PL (Artix-7 Fabric)"
E[AXI4-Stream to VGA] --> F[Vector Generator]
C --> G[Register File]
G --> H[Collision Detector]
H --> I[Sprite Renderer]
F --> J[HDMI Output]
I --> J
D --> K[DAC / Audio Jack]
end
A -- Game Logic Updates --> C
D --> K
| OS / Platform | Compatibility | Status | Requires |
|---|---|---|---|
| 🐧 Linux (Ubuntu 22.04 / Debian) | ✅ Native | Verified | Vivado 2020.2, Serial Terminal (Putty) |
| 🪟 Windows 10/11 | ✅ Vivado Synthesis Only | Supported | Xilinx SDK, USB-JTAG drivers |
| 🍎 macOS (Ventura+) | Synthesis via Docker | Docker, VNC for board setup | |
| 📟 EBAZ4205 Board | ✅ Target Hardware | Verified | 5V Power Supply, JTAG Programmer |
Note: This project does not require a high-end monitor. It targets standard 720p (1280x720) @ 60Hz using the onboard HDMI port of the EBAZ4205.
To load the game onto the board via U-Boot, ensure your SD card is formatted with the FAT32 partition containing the boot files. Connect via UART (115200 baud).
# On your host machine, using a serial terminal (e.g., screen or minicom)
sudo screen /dev/ttyUSB0 115200
# Once U-Boot prompt appears (Hit any key to stop autoboot)
=> fatload mmc 0:1 0x10000000 BOOT.BIN
=> fatload mmc 0:1 0x10000000 devicetree.dtb
=> bootm 0x10000000
# The game should start immediately on the HDMI output.
# Use the physical GPIO buttons (connected to PL) to start a game.If you are building from source, you can modify the hardware profile in the orbital_config.h file within the PS software project. This allows you to tweak the game's feel without touching the Verilog.
/* orbital_config.h - Example Profile for "Twitch Gamer" */
#ifndef ORBITAL_CONFIG_H
#define ORBITAL_CONFIG_H
// Define the number of Enemy Sprite Types (Impacts LUT usage)
#define MAX_ENEMY_TYPES 4
// Vector refresh rate (1 = 60Hz, 2 = 30Hz for smoother vectors)
#define VECTOR_OVERCLOCK_DIVIDER 1
// Sound profile: 0 = 8-bit Arcade, 1 = 16-bit HiFi
#define SOUND_DEPTH 1
// Difficulty scaling multiplier (0-100)
#define DIFFICULTY_AGGRESSION 75
#endif- 📐 Responsive Hardware Logic: The game's difficulty dynamically adjusts based on the number of unused LUTs in the FPGA fabric. A true "responsive" UI that reacts to silicon availability.
- 🌐 Multilingual Text Generation (Bitstream Level): The font ROM includes pre-rasterized glyphs for English, Japanese (Katakana for "Game Over"), and German. Switch via dip-switch on the board.
- 🕰️ 24/7 Customer Support (Silicon Style): This is a hardware project. The "support" is the waveform. We provide detailed simulation testbenches for every Verilog module. Debugging is an experience.
- 🤖 OpenAI & Claude API Integration (Optional PS Feature):
The ARM core can optionally connect to WiFi (via USB dongle) to fetch a "Daily Challenge" seed from an OpenAI or Claude API endpoint. This generates a unique enemy pattern for every session.
- OpenAI: Used for procedural background storytelling.
- Claude: Used for strategic analysis of your gameplay (high scores only).
- 🚫 Anti-Piracy Hardware Lock: (Disclaimer: Not a real DRM). The game will enter a "Demo Loop" mode if it detects a modified bitstream, displaying a rotating cube of shame.
This repository is optimized for ZYNQ FPGA development, retro arcade reconstruction, Verilog VGA generation, EBAZ4205 game porting, hardware description language projects, and bare-metal ARM gaming. The synthesis process utilizes Vivado HLx, targeting the XC7Z010 chip. The sound engine uses I2S protocol for high-fidelity audio mixing.
Hardware Risk: This project involves programming an FPGA board. Incorrect voltage levels, improper JTAG connections, or synthesis of unstable logic may cause permanent damage to your EBAZ4205 board or connected peripherals. The authors and contributors assume no liability for any damage to hardware, data loss, or mental anguish caused by debugging a non-functional always @(posedge clk) block.
Content Disclaimer: The game is a non-commercial, educational art project inspired by the aesthetic of arcade games from the early 1980s. It is not affiliated with, endorsed by, or connected to any current trademark holders of classic arcade titles.
This project is licensed under the MIT License - a permissive license for open-source hardware and software.
You are free to:
- Use the code for commercial and private purposes.
- Modify the Verilog and C source code.
- Distribute compiled bitstreams.
You cannot:
- Hold the authors liable for hardware damage.
- Claim the original bitstream as your own without attribution (though we encourage forks!).
- Use the project to build dangerous hardware without adding safety margins (this is a toy, not a medical device).
- The EBAZ4205 Community for providing a cheap, robust platform for FPGA experimentation.
- Xilinx (AMD) for Vivado, despite its GUI quirks.
- The ghosts of arcade engineers past, who did more with 7400 series logic than we do with modern FPGAs.
Year of Release: 2026. Built for the past, compiled for the future.