Integrate with FuseSoC and Edalize

[taichi-ishitani]

This is an feedback from @olofk.

• FuseSoC
  • https://github.com/olofk/fusesoc
• Edalize
  • https://github.com/olofk/edalize

[taichi-ishitani]

I think FLGen can output file and tool-options fields of EDMA.

• https://edalize.readthedocs.io/en/latest/edam/api.html#file
• https://edalize.readthedocs.io/en/latest/edam/api.html#tool-options

How can I export macro definitions and include direcotries? Using tool-options?

[taichi-ishitani]

How can I export macro definitions and include direcotries? Using tool-options?

@olofk,
Do you have any proposal?

[olofk]

You could use tool_options for both these, but then you would need to implement that for every tool. And some tools don't support setting that as tool options. The EDAM format has abstractions for both these already.

For macro definitions you should be looking at the parameter section where you can define plusargs, generics, verilog parameters and verilog defines.

The EDAM format doesn't use include directories but instead does things like IP-XACT by marking files with the attribute is_include_file : true. It is then up to the backends (in Edalize) to decide how to handle include files. Some tools want include files to be added just like other files and other tools require the opposite.

[olofk]

Here is an example of and EDAM file that FuseSoC has produced for Servant, the reference platform for the SERV CPU. Many of these fields are optional so you don't need to care about them, but you can see an example of how e.g. parameters work

dependencies:
  ::serv:1.2.1: []
  ::servant:1.2.1:
  - ::serv:1.2.1
files:
- core: ::serv:1.2.1
  file_type: vlt
  name: src/serv_1.2.1/data/verilator_waiver.vlt
- core: ::serv:1.2.1
  file_type: verilogSource
  name: src/serv_1.2.1/rtl/serv_bufreg.v
- core: ::serv:1.2.1
  file_type: verilogSource
  name: src/serv_1.2.1/rtl/serv_bufreg2.v
- core: ::serv:1.2.1
  file_type: verilogSource
  name: src/serv_1.2.1/rtl/serv_alu.v
- core: ::serv:1.2.1
  file_type: verilogSource
  name: src/serv_1.2.1/rtl/serv_csr.v
- core: ::serv:1.2.1
  file_type: verilogSource
  name: src/serv_1.2.1/rtl/serv_ctrl.v
- core: ::serv:1.2.1
  file_type: verilogSource
  name: src/serv_1.2.1/rtl/serv_decode.v
- core: ::serv:1.2.1
  file_type: verilogSource
  name: src/serv_1.2.1/rtl/serv_immdec.v
- core: ::serv:1.2.1
  file_type: verilogSource
  name: src/serv_1.2.1/rtl/serv_mem_if.v
- core: ::serv:1.2.1
  file_type: verilogSource
  name: src/serv_1.2.1/rtl/serv_rf_if.v
- core: ::serv:1.2.1
  file_type: verilogSource
  name: src/serv_1.2.1/rtl/serv_rf_ram_if.v
- core: ::serv:1.2.1
  file_type: verilogSource
  name: src/serv_1.2.1/rtl/serv_rf_ram.v
- core: ::serv:1.2.1
  file_type: verilogSource
  name: src/serv_1.2.1/rtl/serv_state.v
- core: ::serv:1.2.1
  file_type: verilogSource
  name: src/serv_1.2.1/rtl/serv_top.v
- core: ::serv:1.2.1
  file_type: verilogSource
  name: src/serv_1.2.1/rtl/serv_rf_top.v
- core: ::serv:1.2.1
  file_type: verilogSource
  name: src/serv_1.2.1/rtl/serv_aligner.v
- core: ::serv:1.2.1
  file_type: verilogSource
  name: src/serv_1.2.1/rtl/serv_compdec.v
- core: ::servant:1.2.1
  file_type: verilogSource
  name: src/servant_1.2.1/servant/servant_clock_gen.v
- core: ::servant:1.2.1
  file_type: verilogSource
  name: src/servant_1.2.1/servant/servant_timer.v
- core: ::servant:1.2.1
  file_type: verilogSource
  name: src/servant_1.2.1/servant/servant_gpio.v
- core: ::servant:1.2.1
  file_type: verilogSource
  name: src/servant_1.2.1/servant/servant_arbiter.v
- core: ::servant:1.2.1
  file_type: verilogSource
  name: src/servant_1.2.1/servant/servant_mux.v
- core: ::servant:1.2.1
  file_type: verilogSource
  name: src/servant_1.2.1/servant/servant_ram.v
- core: ::servant:1.2.1
  file_type: verilogSource
  name: src/servant_1.2.1/servant/servant.v
- core: ::servant:1.2.1
  file_type: verilogSource
  name: src/servant_1.2.1/bench/servant_sim.v
- core: ::servant:1.2.1
  file_type: cppSource
  name: src/servant_1.2.1/bench/servant_tb.cpp
flow_options: {}
hooks: {}
name: servant_1.2.1
parameters:
  RISCV_FORMAL:
    datatype: bool
    paramtype: vlogdefine
  SERV_CLEAR_RAM:
    datatype: bool
    paramtype: vlogdefine
  align:
    datatype: int
    description: Enable/Disable the Misaligned access of instruction
    paramtype: vlogparam
  compressed:
    datatype: int
    description: Enable/Disable the Compressed extension
    paramtype: vlogparam
  firmware:
    datatype: file
    default: /home/olof/projects/serv/workspace/zephyr_phil_24.vh
    description: Preload RAM with a hex file at runtime (overrides memfile)
    paramtype: plusarg
  memsize:
    datatype: int
    default: 32768
    description: Memory size in bytes for RAM (default 8kiB)
    paramtype: vlogparam
  signature:
    datatype: file
    paramtype: plusarg
  timeout:
    datatype: int
    paramtype: plusarg
  uart_baudrate:
    datatype: int
    default: 55600
    description: Treat q output as an UART with the specified baudrate (0 or omitted
      parameter disables UART decoding)
    paramtype: plusarg
  vcd:
    datatype: bool
    paramtype: plusarg
  vcd_start:
    datatype: int
    description: Delay start of VCD dumping until the specified time
    paramtype: plusarg
  with_csr:
    datatype: int
    default: 1
    description: Enable/Disable CSR support
    paramtype: vlogparam
tool_options:
  verilator:
    verilator_options:
    - --trace
toplevel: servant_sim
version: 0.2.1
vpi: []

[taichi-ishitani]

@olofk ,
Thank you for your advice!
My questions are almost cleared but I have an another question about is_include_file attribute.

A SystemVerilog package may be implemented like below.

package foo_bar_pkg;
  `include "foo.svh"
  `include "bar.svh"
endpackage

In this case, do I need to add foo.svh and bar.svh to the files section with is_include_file: true attribute?