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feat(planewatcher): revise rev 1.3 ADC buffer stages - #10

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change_op_amps
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feat(planewatcher): revise rev 1.3 ADC buffer stages#10
mikenye wants to merge 4 commits into
mainfrom
change_op_amps

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@mikenye

@mikenye mikenye commented Jul 31, 2026 •
edited by github-actions Bot
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  • replace the OPA2320 with separate ADA4807-1 and OPA320 buffers
  • update schematics, symbols, PCB placement, and routing
  • refresh the op-amp datasheets
  • document the new buffer architecture and update the board render

🔍 KiCad visual diff

Structural change detected by kicadiff.

Run: https://github.com/plane-watch/hardware/actions/runs/30986303800

Full report with images: download artifact

Structural diff 
planewatcher/kicad/planewatcher.kicad_sch (sch): +0 -10 ~0 =19
  - #FLG04/1 PWR_FLAG [power:PWR_FLAG] at (73.66,143.51)
  - #FLG05/1 PWR_FLAG [power:PWR_FLAG] at (73.66,186.69)
  - #FLG07/1 PWR_FLAG [power:PWR_FLAG] at (73.66,189.23)
  - #FLG08/1 PWR_FLAG [power:PWR_FLAG] at (19.05,140.97)
  - #PWR016/1 GND [power:GND] at (19.05,146.05)
  - #PWR017/1 GND [power:GND] at (73.66,146.05)
  - #PWR018/1 GND [power:GND] at (77.47,171.45)
  - #PWR019/1 GND [power:GND] at (130.81,171.45)
  - J4/1 FPGA BANK 33 [Connector_Generic:Conn_02x20_Odd_Even] at (45.72,166.37)
  - J5/1 FPGA BANK 35 V1.2/V1.3 [Connector_Generic:Conn_02x20_Odd_Even] at (106.68,166.37)
planewatcher/kicad/planewatcher.kicad_pcb (pcb): +9 -1 ~24 =147
  + C1 10nF [Capacitor_SMD:C_0402_1005Metric] at (125.69,66.44)
  + C10 10nF [Capacitor_SMD:C_0402_1005Metric] at (125.69,67.35)
  + C11 10nF [Capacitor_SMD:C_0603_1608Metric] at (132.20,72.26)
  + C12 10nF [Capacitor_SMD:C_0603_1608Metric] at (134.72,72.26)
  + C13 10nF [Capacitor_SMD:C_0402_1005Metric] at (137.27,72.16)
  + C14 10nF [Capacitor_SMD:C_0402_1005Metric] at (139.81,72.16)
  + C81 10µF [Capacitor_SMD:C_0603_1608Metric] at (139.82,77.03)
  + C82 0.1µF [Capacitor_SMD:C_0402_1005Metric] at (139.53,78.23)
  + U12 ADA4807-1 [Package_TO_SOT_SMD:SOT-23-6] at (139.93,88.64)
  - TP13 VLOG_OUT [TestPoint:TestPoint_THTPad_D1.0mm_Drill0.5mm] at (136.39,89.57)
  ~ C2  value: 100nF → 0.1µF
  ~ C9  pos: 143.75,88.36 → 139.91,83.81
  ~ C22  value: 100nF → 0.1µF
  ~ C29  value: 100nF → 0.1µF
  ~ C35  value: 100nF → 0.1µF
  ~ C40  value: 100nF → 0.1µF
  ~ C44  value: 100nF → 0.1µF
  ~ C46  value: 100nF → 0.1µF
  ~ C48  value: 100nF → 0.1µF
  ~ C50  value: 100nF → 0.1µF
  ~ C51  value: 100nF → 0.1µF
  ~ C53  value: 100nF → 0.1µF
  ~ C54  value: 100nF → 0.1µF
  ~ C56  value: 100nF → 0.1µF
  ~ C57  value: 100nF → 0.1µF
  ~ C60  value: 100nF → 0.1µF
  ~ C62  value: 100nF → 0.1µF
  ~ C65  value: 100nF → 0.1µF
  ~ C83  value: 100nF → 0.1µF
  ~ R3  pos: 144.53,90.43 → 142.22,82.43
  ~ R51  pos: 142.97,89.97 → 138.40,85.78, angle: 180 → -90
  ~ REF**  pos: 119.38,68.11 → 115.85,67.86
  ~ TP2  pos: 143.97,86.38 → 143.72,81.94
  ~ U3  value: OPA2320 → OPA320, libId: planewatcher:OPA2320 DRG0008A → Package_TO_SOT_SMD:SOT-23-5, pos: 140.10,88.67 → 140.00,80.78, angle:  → 90
  Nets: +32 -32 ~43
    + /FPGA Headers Bank 33/FPGA_AA21
    + /FPGA Headers Bank 33/FPGA_AA22
    + /FPGA Headers Bank 33/FPGA_AB20
    + /FPGA Headers Bank 33/FPGA_T22
    + /FPGA Headers Bank 33/FPGA_V22
    + /FPGA Headers Bank 33/FPGA_Y20
    + /FPGA Headers Bank 35/FPGA_A16
    + /FPGA Headers Bank 35/FPGA_A17
    + /FPGA Headers Bank 35/FPGA_B15
    + /FPGA Headers Bank 35/FPGA_B16
    + /FPGA Headers Bank 35/FPGA_B17
    + /FPGA Headers Bank 35/FPGA_B21
    + /FPGA Headers Bank 35/FPGA_B22
    + /FPGA Headers Bank 35/FPGA_C15
    + /FPGA Headers Bank 35/FPGA_C17
    + /FPGA Headers Bank 35/FPGA_C18
    + /FPGA Headers Bank 35/FPGA_C20
    + /FPGA Headers Bank 35/FPGA_C22
    + /FPGA Headers Bank 35/FPGA_D16
    + /FPGA Headers Bank 35/FPGA_D17
    + /FPGA Headers Bank 35/FPGA_D20
    + /FPGA Headers Bank 35/FPGA_D22
    + /FPGA Headers Bank 35/FPGA_E18
    + /FPGA Headers Bank 35/FPGA_E19
    + /FPGA Headers Bank 35/FPGA_E20
    + /FPGA Headers Bank 35/FPGA_F17
    + /FPGA Headers Bank 35/FPGA_F18
    + /FPGA Headers Bank 35/FPGA_F19
    + /FPGA Headers Bank 35/FPGA_G15
    + /FPGA Headers Bank 35/FPGA_G17
    + /FPGA Headers Bank 35/FPGA_G19
    + Net-(U3-+IN)
    - /FPGA_A16
    - /FPGA_A17
    - /FPGA_AA21
    - /FPGA_AA22
    - /FPGA_AB20
    - /FPGA_B15
    - /FPGA_B16
    - /FPGA_B17
    - /FPGA_B21
    - /FPGA_B22
    - /FPGA_C15
    - /FPGA_C17
    - /FPGA_C18
    - /FPGA_C20
    - /FPGA_C22
    - /FPGA_D16
    - /FPGA_D17
    - /FPGA_D20
    - /FPGA_D22
    - /FPGA_E18
    - /FPGA_E19
    - /FPGA_E20
    - /FPGA_F17
    - /FPGA_F18
    - /FPGA_F19
    - /FPGA_G15
    - /FPGA_G17
    - /FPGA_G19
    - /FPGA_T22
    - /FPGA_V22
    - /FPGA_Y20
    - Net-(U3B-+INB)
    ~ C9.1: Net-(U3B-+INB) → Net-(U3-+IN)
    ~ J4.2: /FPGA_T22 → /FPGA Headers Bank 33/FPGA_T22
    ~ J4.4: /FPGA_V22 → /FPGA Headers Bank 33/FPGA_V22
    ~ J4.6: /FPGA_Y20 → /FPGA Headers Bank 33/FPGA_Y20
    ~ J4.8: /FPGA_AA22 → /FPGA Headers Bank 33/FPGA_AA22
    ~ J4.10: /FPGA_AA21 → /FPGA Headers Bank 33/FPGA_AA21
    ~ J4.12: /FPGA_AB20 → /FPGA Headers Bank 33/FPGA_AB20
    ~ J5.9: /FPGA_E18 → /FPGA Headers Bank 35/FPGA_E18
    ~ J5.10: /FPGA_F18 → /FPGA Headers Bank 35/FPGA_F18
    ~ J5.11: /FPGA_F17 → /FPGA Headers Bank 35/FPGA_F17
    ~ J5.12: /FPGA_G17 → /FPGA Headers Bank 35/FPGA_G17
    ~ J5.13: /FPGA_C17 → /FPGA Headers Bank 35/FPGA_C17
    ~ J5.14: /FPGA_C18 → /FPGA Headers Bank 35/FPGA_C18
    ~ J5.15: /FPGA_G19 → /FPGA Headers Bank 35/FPGA_G19
    ~ J5.16: /FPGA_F19 → /FPGA Headers Bank 35/FPGA_F19
    ~ J5.17: /FPGA_E20 → /FPGA Headers Bank 35/FPGA_E20
    ~ J5.18: /FPGA_E19 → /FPGA Headers Bank 35/FPGA_E19
    ~ J5.19: /FPGA_D22 → /FPGA Headers Bank 35/FPGA_D22
    ~ J5.20: /FPGA_C22 → /FPGA Headers Bank 35/FPGA_C22
    ~ J5.21: /FPGA_B22 → /FPGA Headers Bank 35/FPGA_B22
    ~ J5.22: /FPGA_B21 → /FPGA Headers Bank 35/FPGA_B21
    ~ J5.23: /FPGA_B17 → /FPGA Headers Bank 35/FPGA_B17
    ~ J5.24: /FPGA_B16 → /FPGA Headers Bank 35/FPGA_B16
    ~ J5.25: /FPGA_A17 → /FPGA Headers Bank 35/FPGA_A17
    ~ J5.26: /FPGA_A16 → /FPGA Headers Bank 35/FPGA_A16
    ~ J5.27: /FPGA_D20 → /FPGA Headers Bank 35/FPGA_D20
    ~ J5.28: /FPGA_C20 → /FPGA Headers Bank 35/FPGA_C20
    ~ J5.29: /FPGA_B15 → /FPGA Headers Bank 35/FPGA_B15
    ~ J5.30: /FPGA_C15 → /FPGA Headers Bank 35/FPGA_C15
    ~ J5.31: /FPGA_D17 → /FPGA Headers Bank 35/FPGA_D17
    ~ J5.32: /FPGA_D16 → /FPGA Headers Bank 35/FPGA_D16
    ~ J5.39: /FPGA_G15 → /FPGA Headers Bank 35/FPGA_G15
    ~ R3.1: Net-(U3B-+INB) → Net-(U3-+IN)
    ~ R51.1: Net-(U3B-+INB) → Net-(U3-+IN)
    ~ TP2.1: Net-(U3B-+INB) → Net-(U3-+IN)
    ~ U3.1: Net-(RN1D-R4.2) → Net-(RN1A-R1.2)
    ~ U3.2: Net-(RN1D-R4.2) → GND
    ~ U3.3: /ADC_Driver/VLOG_IN → Net-(U3-+IN)
    ~ U3.4: GND → Net-(RN1A-R1.2)
    ~ U3.5: Net-(U3B-+INB) → 3V3
    ~ U3.6: Net-(RN1A-R1.2) → (unconnected)
    ~ U3.7: Net-(RN1A-R1.2) → (unconnected)
    ~ U3.8: 3V3 → (unconnected)

@mikenye
feat(planewatcher): revise rev 1.3 ADC buffer stages
abbfd7a 
- replace the OPA2320 with separate ADA4807-1 and OPA320 buffers
- update schematics, symbols, PCB placement, and routing
- refresh the op-amp datasheets
- document the new buffer architecture and update the board render
@mikenye mikenye added this to the proto rev 1.3 milestone Jul 31, 2026
@mikenye
mikenye requested a review from shaneshort July 31, 2026 13:32
@mikenye mikenye self-assigned this Jul 31, 2026
@mikenye mikenye added documentation Improvements or additions to documentation enhancement New feature or request labels Jul 31, 2026
@github-actions

github-actions Bot commented Jul 31, 2026 •
edited
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🔍 KiCad visual diff

Structural change detected by kicadiff.

Run: https://github.com/plane-watch/hardware/actions/runs/30986303800

Full report with images: download artifact

Structural diff 
planewatcher/kicad/planewatcher.kicad_sch (sch): +0 -10 ~0 =19
  - #FLG04/1 PWR_FLAG [power:PWR_FLAG] at (73.66,143.51)
  - #FLG05/1 PWR_FLAG [power:PWR_FLAG] at (73.66,186.69)
  - #FLG07/1 PWR_FLAG [power:PWR_FLAG] at (73.66,189.23)
  - #FLG08/1 PWR_FLAG [power:PWR_FLAG] at (19.05,140.97)
  - #PWR016/1 GND [power:GND] at (19.05,146.05)
  - #PWR017/1 GND [power:GND] at (73.66,146.05)
  - #PWR018/1 GND [power:GND] at (77.47,171.45)
  - #PWR019/1 GND [power:GND] at (130.81,171.45)
  - J4/1 FPGA BANK 33 [Connector_Generic:Conn_02x20_Odd_Even] at (45.72,166.37)
  - J5/1 FPGA BANK 35 V1.2/V1.3 [Connector_Generic:Conn_02x20_Odd_Even] at (106.68,166.37)
planewatcher/kicad/planewatcher.kicad_pcb (pcb): +9 -1 ~24 =147
  + C1 10nF [Capacitor_SMD:C_0402_1005Metric] at (125.69,66.44)
  + C10 10nF [Capacitor_SMD:C_0402_1005Metric] at (125.69,67.35)
  + C11 10nF [Capacitor_SMD:C_0603_1608Metric] at (132.20,72.26)
  + C12 10nF [Capacitor_SMD:C_0603_1608Metric] at (134.72,72.26)
  + C13 10nF [Capacitor_SMD:C_0402_1005Metric] at (137.27,72.16)
  + C14 10nF [Capacitor_SMD:C_0402_1005Metric] at (139.81,72.16)
  + C81 10µF [Capacitor_SMD:C_0603_1608Metric] at (139.82,77.03)
  + C82 0.1µF [Capacitor_SMD:C_0402_1005Metric] at (139.53,78.23)
  + U12 ADA4807-1 [Package_TO_SOT_SMD:SOT-23-6] at (139.93,88.64)
  - TP13 VLOG_OUT [TestPoint:TestPoint_THTPad_D1.0mm_Drill0.5mm] at (136.39,89.57)
  ~ C2  value: 100nF → 0.1µF
  ~ C9  pos: 143.75,88.36 → 139.91,83.81
  ~ C22  value: 100nF → 0.1µF
  ~ C29  value: 100nF → 0.1µF
  ~ C35  value: 100nF → 0.1µF
  ~ C40  value: 100nF → 0.1µF
  ~ C44  value: 100nF → 0.1µF
  ~ C46  value: 100nF → 0.1µF
  ~ C48  value: 100nF → 0.1µF
  ~ C50  value: 100nF → 0.1µF
  ~ C51  value: 100nF → 0.1µF
  ~ C53  value: 100nF → 0.1µF
  ~ C54  value: 100nF → 0.1µF
  ~ C56  value: 100nF → 0.1µF
  ~ C57  value: 100nF → 0.1µF
  ~ C60  value: 100nF → 0.1µF
  ~ C62  value: 100nF → 0.1µF
  ~ C65  value: 100nF → 0.1µF
  ~ C83  value: 100nF → 0.1µF
  ~ R3  pos: 144.53,90.43 → 142.22,82.43
  ~ R51  pos: 142.97,89.97 → 138.40,85.78, angle: 180 → -90
  ~ REF**  pos: 119.38,68.11 → 115.85,67.86
  ~ TP2  pos: 143.97,86.38 → 143.72,81.94
  ~ U3  value: OPA2320 → OPA320, libId: planewatcher:OPA2320 DRG0008A → Package_TO_SOT_SMD:SOT-23-5, pos: 140.10,88.67 → 140.00,80.78, angle:  → 90
  Nets: +32 -32 ~43
    + /FPGA Headers Bank 33/FPGA_AA21
    + /FPGA Headers Bank 33/FPGA_AA22
    + /FPGA Headers Bank 33/FPGA_AB20
    + /FPGA Headers Bank 33/FPGA_T22
    + /FPGA Headers Bank 33/FPGA_V22
    + /FPGA Headers Bank 33/FPGA_Y20
    + /FPGA Headers Bank 35/FPGA_A16
    + /FPGA Headers Bank 35/FPGA_A17
    + /FPGA Headers Bank 35/FPGA_B15
    + /FPGA Headers Bank 35/FPGA_B16
    + /FPGA Headers Bank 35/FPGA_B17
    + /FPGA Headers Bank 35/FPGA_B21
    + /FPGA Headers Bank 35/FPGA_B22
    + /FPGA Headers Bank 35/FPGA_C15
    + /FPGA Headers Bank 35/FPGA_C17
    + /FPGA Headers Bank 35/FPGA_C18
    + /FPGA Headers Bank 35/FPGA_C20
    + /FPGA Headers Bank 35/FPGA_C22
    + /FPGA Headers Bank 35/FPGA_D16
    + /FPGA Headers Bank 35/FPGA_D17
    + /FPGA Headers Bank 35/FPGA_D20
    + /FPGA Headers Bank 35/FPGA_D22
    + /FPGA Headers Bank 35/FPGA_E18
    + /FPGA Headers Bank 35/FPGA_E19
    + /FPGA Headers Bank 35/FPGA_E20
    + /FPGA Headers Bank 35/FPGA_F17
    + /FPGA Headers Bank 35/FPGA_F18
    + /FPGA Headers Bank 35/FPGA_F19
    + /FPGA Headers Bank 35/FPGA_G15
    + /FPGA Headers Bank 35/FPGA_G17
    + /FPGA Headers Bank 35/FPGA_G19
    + Net-(U3-+IN)
    - /FPGA_A16
    - /FPGA_A17
    - /FPGA_AA21
    - /FPGA_AA22
    - /FPGA_AB20
    - /FPGA_B15
    - /FPGA_B16
    - /FPGA_B17
    - /FPGA_B21
    - /FPGA_B22
    - /FPGA_C15
    - /FPGA_C17
    - /FPGA_C18
    - /FPGA_C20
    - /FPGA_C22
    - /FPGA_D16
    - /FPGA_D17
    - /FPGA_D20
    - /FPGA_D22
    - /FPGA_E18
    - /FPGA_E19
    - /FPGA_E20
    - /FPGA_F17
    - /FPGA_F18
    - /FPGA_F19
    - /FPGA_G15
    - /FPGA_G17
    - /FPGA_G19
    - /FPGA_T22
    - /FPGA_V22
    - /FPGA_Y20
    - Net-(U3B-+INB)
    ~ C9.1: Net-(U3B-+INB) → Net-(U3-+IN)
    ~ J4.2: /FPGA_T22 → /FPGA Headers Bank 33/FPGA_T22
    ~ J4.4: /FPGA_V22 → /FPGA Headers Bank 33/FPGA_V22
    ~ J4.6: /FPGA_Y20 → /FPGA Headers Bank 33/FPGA_Y20
    ~ J4.8: /FPGA_AA22 → /FPGA Headers Bank 33/FPGA_AA22
    ~ J4.10: /FPGA_AA21 → /FPGA Headers Bank 33/FPGA_AA21
    ~ J4.12: /FPGA_AB20 → /FPGA Headers Bank 33/FPGA_AB20
    ~ J5.9: /FPGA_E18 → /FPGA Headers Bank 35/FPGA_E18
    ~ J5.10: /FPGA_F18 → /FPGA Headers Bank 35/FPGA_F18
    ~ J5.11: /FPGA_F17 → /FPGA Headers Bank 35/FPGA_F17
    ~ J5.12: /FPGA_G17 → /FPGA Headers Bank 35/FPGA_G17
    ~ J5.13: /FPGA_C17 → /FPGA Headers Bank 35/FPGA_C17
    ~ J5.14: /FPGA_C18 → /FPGA Headers Bank 35/FPGA_C18
    ~ J5.15: /FPGA_G19 → /FPGA Headers Bank 35/FPGA_G19
    ~ J5.16: /FPGA_F19 → /FPGA Headers Bank 35/FPGA_F19
    ~ J5.17: /FPGA_E20 → /FPGA Headers Bank 35/FPGA_E20
    ~ J5.18: /FPGA_E19 → /FPGA Headers Bank 35/FPGA_E19
    ~ J5.19: /FPGA_D22 → /FPGA Headers Bank 35/FPGA_D22
    ~ J5.20: /FPGA_C22 → /FPGA Headers Bank 35/FPGA_C22
    ~ J5.21: /FPGA_B22 → /FPGA Headers Bank 35/FPGA_B22
    ~ J5.22: /FPGA_B21 → /FPGA Headers Bank 35/FPGA_B21
    ~ J5.23: /FPGA_B17 → /FPGA Headers Bank 35/FPGA_B17
    ~ J5.24: /FPGA_B16 → /FPGA Headers Bank 35/FPGA_B16
    ~ J5.25: /FPGA_A17 → /FPGA Headers Bank 35/FPGA_A17
    ~ J5.26: /FPGA_A16 → /FPGA Headers Bank 35/FPGA_A16
    ~ J5.27: /FPGA_D20 → /FPGA Headers Bank 35/FPGA_D20
    ~ J5.28: /FPGA_C20 → /FPGA Headers Bank 35/FPGA_C20
    ~ J5.29: /FPGA_B15 → /FPGA Headers Bank 35/FPGA_B15
    ~ J5.30: /FPGA_C15 → /FPGA Headers Bank 35/FPGA_C15
    ~ J5.31: /FPGA_D17 → /FPGA Headers Bank 35/FPGA_D17
    ~ J5.32: /FPGA_D16 → /FPGA Headers Bank 35/FPGA_D16
    ~ J5.39: /FPGA_G15 → /FPGA Headers Bank 35/FPGA_G15
    ~ R3.1: Net-(U3B-+INB) → Net-(U3-+IN)
    ~ R51.1: Net-(U3B-+INB) → Net-(U3-+IN)
    ~ TP2.1: Net-(U3B-+INB) → Net-(U3-+IN)
    ~ U3.1: Net-(RN1D-R4.2) → Net-(RN1A-R1.2)
    ~ U3.2: Net-(RN1D-R4.2) → GND
    ~ U3.3: /ADC_Driver/VLOG_IN → Net-(U3-+IN)
    ~ U3.4: GND → Net-(RN1A-R1.2)
    ~ U3.5: Net-(U3B-+INB) → 3V3
    ~ U3.6: Net-(RN1A-R1.2) → (unconnected)
    ~ U3.7: Net-(RN1A-R1.2) → (unconnected)
    ~ U3.8: 3V3 → (unconnected)

mikenye added 3 commits July 31, 2026 21:35
@mikenye
update pcb fields to match schematic
4f5c04e
@mikenye
add six 10 nF C0G return-path capacitors to spare Bank 33 pins
e6a7331 
- move the Bank 33 and Bank 35 headers into dedicated schematic sheets
- update the PCB routing and project configuration
- preserve the original physical positions of J4 and J5
@mikenye
Adjust component grouping
6483038
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@shaneshort shaneshort Awaiting requested review from shaneshort

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@mikenye mikenye

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proto rev 1.3

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@mikenye