test: coverage uplift for v0.1.1 diff (regalloc, M7 profiles, CLI)

[avrabe]

Summary

Backfills patch coverage for the v0.1.1 diff that landed as #86 (commit 5c7ef0c). The same codecov/patch threshold would block the next stacked PR (#87, RISC-V skeleton) — this PR lands the missing tests so the gate clears without waivers.

37 new tests, no production-code changes.

What's covered

• synth-core/target.rs — imxrt1062() and stm32h743() constructors (5 tests): arch enum, MPU region count, FPU precision, flash/ram sizing, target_triple/cpu_name/has_hardware_fp, plus a regression guard that M4 reports 8 regions while M7-class reports 16.
• synth-synthesis/instruction_selector.rs (15 tests):
  • compute_local_layout: zero-frame for params-only; single i32; single i64; mixed i32+i64 with 8-byte alignment edge case; param-index skipping.
  • infer_i64_locals: LocalSet, LocalTee, no-flag-on-i32, propagation through i64 arith.
  • alloc_consecutive_pair: basic consecutiveness contract, extra_avoid skip, implicit-hi-of-stack-i64 reservation (the bug class the PR fixed).
  • select_with_stack: emits matching sub sp/add sp frame ops for i64 locals; omits frame when only params used; i32 locals use Str/Ldr to SP-relative slots.
• synth-synthesis/optimizer_bridge.rs (6 tests, all driving ir_to_arm):
  • I64Const with num_params=4 does NOT target R0..R3 via Movw/Movt (the AAPCS-clobber bug).
  • I64Const with num_params=2 does NOT target R0/R1.
  • I64Const with num_params=0 uses a callee-saved pair.
  • I64Add emits Adds + Adc from the operand regs (not hardcoded R0:R1/R2:R3).
  • I64Sub emits Subs + Sbc.
  • I64Or emits two Orr instructions.
• synth-cli/main.rs (9 unit tests):
  • target_info_command for imxrt1062 and stm32h743 success paths.
  • target_info_command unknown-target error advertises all four supported names.
  • synthesize_command --hardware string→ctor dispatch covered.
  • resolve_target_spec: default (Arm32 ISA), --cortex-m flag (M3), explicit target wins, unknown triple errors with help text.
• synth-cli/tests/wast_compile.rs (2 integration tests):
  • --relocatable forces ET_REL on import-free wasm.
  • default (no flag, no imports) still produces ET_EXEC.

Test plan

• cargo test --workspace — passes locally (no regressions across the 1000+ existing tests; 37 new tests added).
• cargo clippy --workspace --all-targets -- -D warnings — clean.
• cargo fmt --check — clean.
• CI codecov/patch threshold clears.

🤖 Generated with Claude Code

[codecov]

Codecov Report

❌ Patch coverage is 99.33775% with 3 lines in your changes missing coverage. Please review.

Files with missing lines	Patch %	Lines
crates/synth-cli/src/main.rs	98.18%	1 Missing ⚠️
crates/synth-synthesis/src/instruction_selector.rs	99.39%	1 Missing ⚠️
crates/synth-synthesis/src/optimizer_bridge.rs	99.45%	1 Missing ⚠️

📢 Thoughts on this report? Let us know!