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RISCV: Make analysis function set mnemonic field to enable ROP search (#5952)
* Make analysis function set mnemonic field to enablre ROP search * Add tests
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3 files changed

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-1
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3 files changed

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librz/arch/p/analysis/analysis_riscv_cs.c

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -781,7 +781,7 @@ int analyze_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *buf
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ctx->omode = mode;
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ctx->obits = analysis->bits;
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}
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analysis->pcalign = 2;
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op->addr = addr;
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if (len < 2) {
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return -1;
@@ -1911,6 +1911,10 @@ int analyze_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *buf
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}
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beach:
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if (insn) {
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if (mask & RZ_ANALYSIS_OP_MASK_DISASM) {
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op->mnemonic = rz_str_newf("%s%s%s", insn->mnemonic, insn->op_str[0] ? " " : "", rz_str_get(insn->op_str));
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}
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set_op_sign(op, insn);
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set_op_data_size(op, insn);
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set_op_val(op, insn);

librz/core/rop.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1539,6 +1539,8 @@ static void set_increment_based_on_arch(const RzCore *core, const char *arch, in
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*increment = rz_config_get_i(core->config, "asm.bits") == 16 ? 2 : 4;
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} else if (RZ_STR_EQ(arch, "avr")) { // AVR is halfword aligned.
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*increment = 2;
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} else if (RZ_STR_EQ(arch, "riscv")) {
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*increment = core->analysis->pcalign;
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}
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}
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