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PowerPC: Add vec_min/vec_max support for vector float/double #2167

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fe6f4d9
PowerPC:Add vec_min/vec_max support for vector float/double
lei137 Jun 18, 2026
0c23500
change feature guard to power8-vector as that's when the instructions…
lei137 Jun 18, 2026
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51 changes: 22 additions & 29 deletions crates/core_arch/src/powerpc/altivec.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -230,6 +230,11 @@ unsafe extern "unadjusted" {
#[link_name = "llvm.umin.v4i32"]
fn vminuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;

#[link_name = "llvm.ppc.altivec.vmaxfp"]
fn vmaxfp(a: vector_float, b: vector_float) -> vector_float;
#[link_name = "llvm.ppc.altivec.vminfp"]
fn vminfp(a: vector_float, b: vector_float) -> vector_float;

#[link_name = "llvm.ppc.altivec.vsubsbs"]
fn vsubsbs(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char;
#[link_name = "llvm.ppc.altivec.vsubshs"]
Expand Down Expand Up @@ -411,7 +416,7 @@ unsafe extern "unadjusted" {
}

#[macro_use]
mod sealed {
pub(crate) mod sealed {
use super::*;

#[unstable(feature = "stdarch_powerpc", issue = "111145")]
Expand Down Expand Up @@ -1657,13 +1662,16 @@ mod sealed {
test_impl! { vec_vminuh (a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [vminuh, vminuh] }
test_impl! { vec_vminuw (a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [vminuw, vminuw] }

test_impl! { vec_vminfp (a: vector_float, b: vector_float) -> vector_float [vminfp, vminfp / xvminsp] }

#[unstable(feature = "stdarch_powerpc", issue = "111145")]
pub trait VectorMin<Other> {
type Result;
unsafe fn vec_min(self, b: Other) -> Self::Result;
}

impl_vec_trait! { [VectorMin vec_min] ~(vminub, vminsb, vminuh, vminsh, vminuw, vminsw) }
impl_vec_trait! { [VectorMin vec_min] vec_vminfp(vector_float, vector_float) -> vector_float }

test_impl! { vec_vmaxsb (a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [vmaxsb, vmaxsb] }
test_impl! { vec_vmaxsh (a: vector_signed_short, b: vector_signed_short) -> vector_signed_short [vmaxsh, vmaxsh] }
Expand All @@ -1673,13 +1681,16 @@ mod sealed {
test_impl! { vec_vmaxuh (a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short [vmaxuh, vmaxuh] }
test_impl! { vec_vmaxuw (a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [vmaxuw, vmaxuw] }

test_impl! { vec_vmaxfp (a: vector_float, b: vector_float) -> vector_float [vmaxfp, vmaxfp / xvmaxsp] }

#[unstable(feature = "stdarch_powerpc", issue = "111145")]
pub trait VectorMax<Other> {
type Result;
unsafe fn vec_max(self, b: Other) -> Self::Result;
}

impl_vec_trait! { [VectorMax vec_max] ~(vmaxub, vmaxsb, vmaxuh, vmaxsh, vmaxuw, vmaxsw) }
impl_vec_trait! { [VectorMax vec_max] vec_vmaxfp(vector_float, vector_float) -> vector_float }

#[inline]
#[target_feature(enable = "altivec")]
Expand Down Expand Up @@ -4685,7 +4696,7 @@ mod endian {
pub use self::endian::*;

#[cfg(test)]
mod tests {
pub(crate) mod tests {
use super::*;

use std::mem::transmute;
Expand Down Expand Up @@ -6118,20 +6129,6 @@ mod tests {
[2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0],
[0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2, 0, 0, 1, 2] }

macro_rules! test_vec_min {
{ $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
#[simd_test(enable = "altivec")]
fn $name() {
let a: s_t_l!($ty) = $ty::new($($a),+).into();
let b: s_t_l!($ty) = $ty::new($($b),+).into();

let d = $ty::new($($d),+);
let r = $ty::from(unsafe { vec_min(a, b) });
assert_eq!(d, r);
}
}
}

test_vec_min! { test_vec_min_i32x4, i32x4,
[-1, 0, 1, 2],
[2, 1, -1, -2],
Expand Down Expand Up @@ -6162,19 +6159,10 @@ mod tests {
[2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0],
[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] }

macro_rules! test_vec_max {
{ $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
#[simd_test(enable = "altivec")]
fn $name() {
let a: s_t_l!($ty) = $ty::new($($a),+).into();
let b: s_t_l!($ty) = $ty::new($($b),+).into();

let d = $ty::new($($d),+);
let r = $ty::from(unsafe { vec_max(a, b) });
assert_eq!(d, r);
}
}
}
test_vec_min! { test_vec_min_f32x4, f32x4,
[-1.0, 0.0, 1.0, 2.0],
[2.0, 1.0, -1.0, -2.0],
[-1.0, 0.0, -1.0, -2.0] }

test_vec_max! { test_vec_max_i32x4, i32x4,
[-1, 0, 1, 2],
Expand Down Expand Up @@ -6206,6 +6194,11 @@ mod tests {
[2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0, 2, 1, 0, 0],
[2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2] }

test_vec_max! { test_vec_max_f32x4, f32x4,
[-1.0, 0.0, 1.0, 2.0],
[2.0, 1.0, -1.0, -2.0],
[2.0, 1.0, 1.0, 2.0] }

macro_rules! test_vec_perm {
{$name:ident,
$shorttype:ident, $longtype:ident,
Expand Down
37 changes: 37 additions & 0 deletions crates/core_arch/src/powerpc/macros.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -154,6 +154,9 @@ macro_rules! s_t_l {
(f32x4) => {
vector_float
};
(f64x2) => {
vector_double
};
}

macro_rules! t_t_l {
Expand Down Expand Up @@ -274,10 +277,44 @@ macro_rules! t_b {
};
}

#[cfg(test)]
macro_rules! test_vec_min {
{ $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
#[simd_test(enable = "altivec")]
fn $name() {
let a: s_t_l!($ty) = $ty::new($($a),+).into();
let b: s_t_l!($ty) = $ty::new($($b),+).into();

let d = $ty::new($($d),+);
let r = $ty::from(unsafe { vec_min(a, b) });
assert_eq!(d, r);
}
}
}

#[cfg(test)]
macro_rules! test_vec_max {
{ $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
#[simd_test(enable = "altivec")]
fn $name() {
let a: s_t_l!($ty) = $ty::new($($a),+).into();
let b: s_t_l!($ty) = $ty::new($($b),+).into();

let d = $ty::new($($d),+);
let r = $ty::from(unsafe { vec_max(a, b) });
assert_eq!(d, r);
}
}
}

pub(crate) use impl_vec_trait;
pub(crate) use s_t_l;
pub(crate) use t_b;
pub(crate) use t_t_l;
pub(crate) use t_t_s;
pub(crate) use t_u;
pub(crate) use test_impl;
#[cfg(test)]
pub(crate) use test_vec_max;
#[cfg(test)]
pub(crate) use test_vec_min;
44 changes: 44 additions & 0 deletions crates/core_arch/src/powerpc/vsx.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -59,6 +59,11 @@ unsafe extern "unadjusted" {
b: vector_signed_int,
c: vector_unsigned_char,
) -> vector_signed_int;

#[link_name = "llvm.ppc.vsx.xvmaxdp"]
fn xvmaxdp(a: vector_double, b: vector_double) -> vector_double;
#[link_name = "llvm.ppc.vsx.xvmindp"]
fn xvmindp(a: vector_double, b: vector_double) -> vector_double;
}

mod sealed {
Expand Down Expand Up @@ -171,6 +176,40 @@ mod sealed {
vec_mergeeo! { vector_unsigned_int, mergee, mergeo }
vec_mergeeo! { vector_bool_int, mergee, mergeo }
vec_mergeeo! { vector_float, mergee, mergeo }

#[inline]
#[target_feature(enable = "vsx")]
#[cfg_attr(all(test, target_feature = "power8-vector"), assert_instr(xvmindp))]
unsafe fn vec_xvmindp(a: vector_double, b: vector_double) -> vector_double {
xvmindp(a, b)
}

#[inline]
#[target_feature(enable = "vsx")]
#[cfg_attr(all(test, target_feature = "power8-vector"), assert_instr(xvmaxdp))]
unsafe fn vec_xvmaxdp(a: vector_double, b: vector_double) -> vector_double {
xvmaxdp(a, b)
}

#[unstable(feature = "stdarch_powerpc", issue = "111145")]
impl super::altivec::sealed::VectorMin<vector_double> for vector_double {
type Result = vector_double;
#[inline]
#[target_feature(enable = "vsx")]
unsafe fn vec_min(self, b: vector_double) -> Self::Result {
vec_xvmindp(self, b)
}
}

#[unstable(feature = "stdarch_powerpc", issue = "111145")]
impl super::altivec::sealed::VectorMax<vector_double> for vector_double {
type Result = vector_double;
#[inline]
#[target_feature(enable = "vsx")]
unsafe fn vec_max(self, b: vector_double) -> Self::Result {
vec_xvmaxdp(self, b)
}
}
}

/// Vector permute.
Expand Down Expand Up @@ -234,6 +273,8 @@ mod tests {
use crate::mem::transmute;
use stdarch_test::simd_test;

use super::super::macros::*;

macro_rules! test_vec_xxpermdi {
{$name:ident, $shorttype:ident, $longtype:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
#[simd_test(enable = "vsx")]
Expand All @@ -255,4 +296,7 @@ mod tests {
test_vec_xxpermdi! {test_vec_xxpermdi_i64x2, i64x2, vector_signed_long, [0], [-1], [2], [-3]}
test_vec_xxpermdi! {test_vec_xxpermdi_m64x2, m64x2, vector_bool_long, [false], [true], [false], [true]}
test_vec_xxpermdi! {test_vec_xxpermdi_f64x2, f64x2, vector_double, [0.0], [1.0], [2.0], [3.0]}

test_vec_min! { test_vec_min_f64x2, f64x2, [-1.0, 0.0], [2.0, 1.0], [-1.0, 0.0] }
test_vec_max! { test_vec_max_f64x2, f64x2, [-1.0, 0.0], [2.0, 1.0], [2.0, 1.0] }
}
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