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docs(adr): ADR-083 — per-cluster Pi compute hop (proposed) - #428

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feat/adr-083-cluster-pi-compute-hop
Apr 26, 2026
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docs(adr): ADR-083 — per-cluster Pi compute hop (proposed)#428
ruvnet merged 1 commit into
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feat/adr-083-cluster-pi-compute-hop

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@ruvnet ruvnet commented Apr 26, 2026

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Summary

Adopt one Pi per cluster of 3-6 ESP32-S3 sensor nodes as the canonical RuView mid-scale deployment shape, rather than the full three-tier (dual-MCU + per-node Pi) shape from docs/research/architecture/three-tier-rust-node.md.

This is the L3-hybrid path identified in docs/research/architecture/decision-tree.md §2 — the cheapest viable upgrade. Sensor nodes are unchanged from ADR-028 / ADR-081; the cluster Pi gains the responsibilities the ESP32-S3 cannot carry:

  1. Per-cluster ML inference — WiFlow / DT-Pose / GraphPose-Fi class models (4-10M params, 0.5-1.5 GFLOPs) want a Cortex-A53-class target. ESP32-S3 cannot host these; cloud can but only at the cost of round-trip latency.
  2. QUIC backhaulquinn + rustls is mature on Linux but does not run on ESP32-class hardware in any production-grade form (SOTA §5).
  3. Cluster-level OTA + secure-boot anchor — buildroot + dm-verity + signed FIT on the Pi as the trust anchor for its sensors' rollouts.

Status

Proposed — not committing to implementation. Acceptance gated on:

  1. Cross-compile to aarch64-unknown-linux-gnu / armv7-unknown-linux-gnueabihf with workspace tests passing
  2. 3-sensor + 1-Pi field test demonstrating end-to-end CSI → fusion → cloud at ≤100 ms cluster latency
  3. Cluster-Pi SoC choice ADR (decision-tree.md L6) approved

What this ADR does NOT decide

  • Pi SoC choice (Pi Zero 2W vs CM4 vs Pi 5) — deferred to a future ADR (decision-tree.md L6 / secure-boot threat model).
  • no_std CSI maturity (decision-tree.md L4) — not required for the cluster-Pi shape; only required for dual-MCU.
  • Per-node Pi shape — explicitly not this ADR. Stays as a future option.

Validation in this PR

Test plan

🤖 Generated with claude-flow

Adopt one Pi per cluster of 3-6 ESP32-S3 sensor nodes as the canonical
fleet-shape, rather than the full three-tier (dual-MCU + per-node Pi)
shape. Sensor nodes are unchanged from ADR-028 / ADR-081; the cluster
Pi gains the responsibilities the ESP32-S3 cannot carry — pose-grade
ML inference, QUIC backhaul to gateway/cloud, and a cluster-level OTA
+ secure-boot anchor.

The cluster-Pi shape is the L3-hybrid path identified in
docs/research/architecture/decision-tree.md §2 — the cheapest viable
upgrade. The full three-tier shape remains the long-term exploration
target, gated behind no_std CSI maturity (decision-tree L4) and
per-node ISR-jitter evidence (L2).

Status: Proposed. Acceptance gated on:
1. Cross-compile to aarch64 / armv7 with workspace tests passing
2. 3-sensor + 1-Pi field test demonstrating end-to-end CSI → fusion →
   cloud at <=100 ms cluster latency
3. Cluster-Pi SoC choice ADR (decision-tree L6) approved

References:
- docs/research/architecture/three-tier-rust-node.md (seed exploration)
- docs/research/architecture/decision-tree.md (L3 hybrid path)
- docs/research/sota/2026-Q2-rf-sensing-and-edge-rust.md (SOTA evidence)

Co-Authored-By: claude-flow <ruv@ruv.net>
@ruvnet
ruvnet merged commit 259939b into main Apr 26, 2026
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ruvnet deleted the feat/adr-083-cluster-pi-compute-hop branch April 26, 2026 03:08
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