[JIT Kernel]Support fused_add_rmsnorm in JIT Kernel

[HydraQYH]

Motivation

There are two differences from the Flashinfer implementation:

1. Avoid storing/loading inp+res in shared memory
2. Using 256-bit LDG on B200

Modifications

• python/sglang/jit_kernel/norm.py
• python/sglang/jit_kernel/csrc/elementwise/fused_add_rmsnorm.cuh
• python/sglang/jit_kernel/tests/test_fused_add_rmsnorm.py
• python/sglang/jit_kernel/include/sgl_kernel/vec.cuh

Accuracy Tests

H20(with CUDA 12.9):

B200(witch CUDA 13.1):

Benchmarking and Profiling

H20(with CUDA 12.9):
h20_fused_add_rmsnorm.txt
B200(witch CUDA 13.1):
b200_fused_add_rmsnorm.txt

Checklist

• Format your code according to the Format code with pre-commit.
• Add unit tests according to the Run and add unit tests.
• Update documentation according to Write documentations.
• Provide accuracy and speed benchmark results according to Test the accuracy and Benchmark the speed.
• Follow the SGLang code style guidance.

Review Process

1. Ping Merge Oncalls to start the PR flow. See the PR Merge Process.
2. Get approvals from CODEOWNERS and other reviewers.
3. Trigger CI tests with comments or contact authorized users to do so.
   • /tag-run-ci-label, /rerun-failed-ci, /tag-and-rerun-ci
4. After green CI and required approvals, ask Merge Oncalls to merge.

[gemini-code-assist]

Summary of Changes

Hello @HydraQYH, I'm Gemini Code Assist¹! I'm currently reviewing this pull request and will post my feedback shortly. In the meantime, here's a summary to help you and other reviewers quickly get up to speed!

This pull request introduces a highly optimized JIT kernel for the fused_add_rmsnorm operation, crucial for efficient deep learning model execution. The primary goal is to boost performance by refining memory access patterns and utilizing advanced GPU features like 256-bit global loads, especially beneficial for NVIDIA B200 architectures. The new kernel is seamlessly integrated into the SGLang JIT framework and its correctness is verified through extensive testing against a known performant library.

Highlights

• New Fused Kernel: Implemented a new CUDA kernel (fused_add_rmsnorm.cuh) for a fused add and RMS normalization operation.
• Performance Optimizations: The new kernel is optimized to avoid storing intermediate inp+res results in shared memory and leverages 256-bit global memory loads (LDG) for enhanced performance on B200 GPUs.
• Python Integration: Integrated the new CUDA kernel into the Python JIT kernel system, making it accessible via a new fused_add_rmsnorm function in sglang.jit_kernel.norm.
• Unit Testing: Added comprehensive unit tests (test_fused_add_rmsnorm.py) to verify the numerical accuracy of the new fused operation by comparing its output against the flashinfer library across various input sizes.

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[HydraQYH]

@BBuf @DarkSharpness WIP for now, I will add benchmarks within a few days.

[gemini-code-assist]

Code Review

This pull request introduces a new fused add and RMSNorm JIT kernel, which is a valuable performance optimization. The implementation is generally solid, with corresponding Python bindings and tests. My review identifies a few areas for improvement. There is a high-priority issue in the CUDA kernel regarding an unused and misused kernel parameter that should be addressed. I've also included several medium-severity suggestions to enhance code quality, maintainability, and test coverage. Specifically, I recommend improving const-correctness, reducing code duplication in the CUDA kernel, and expanding the test suite to cover all supported data types and simplify test data generation. Addressing these points will improve the robustness and maintainability of this new feature.

[HydraQYH]

@DarkSharpness @BBuf Ready for review.

[HydraQYH]

/tag-and-rerun-ci

[HydraQYH]

/rerun-failed-ci

[DarkSharpness]

This is actually very tricky. Before B200, the max load/store size is 128bit. On and after B200, the max size is 256bit. On H200, developers may misuse this API and lead to poor performance.

It's okay to keep this behavior. But in the future we need to forbid using 256bit load/store on H200.

[HydraQYH]

Yeah. I think we could use __CUDA_ARCH__ for conditional compilation. However, this macro only works on device code, which might not meet our requirements.