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SiFive Intel FPGA Direction Request#131

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jtarango wants to merge 13 commits intosifive:masterfrom
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SiFive Intel FPGA Direction Request#131
jtarango wants to merge 13 commits intosifive:masterfrom
jtarango:master

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@jtarango
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Hi Team,

I have been working to integrate the SiFive generated processor to a Intel FPGA synthesis, place, and route. Based on the implementation from Xilinx, it does not seem to be an appropriate fit for the tool chain to be partitioned in the current ordering. The code is a demo of what it looks like to integrate into the tcl and a single make file. The current approach I believe it would be best to use a single makefile that takes a file tree input.

Please let me know your thoughts and advice for the best path to integrate. The code in its current state is not ready to push and awaiting a decision from SiFive.

@erikdanie
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Hi Joe,

First off, thanks for the work you've done here!
Are you asking if it is okay to make an entirely new synthesis flow for Altera boards? If so, the answer is yes. The tcl scripts are totally vendor specific, so it doesn't matter at all that one looks like the other.
Does the code here work as is? What boards have you tested it with? I am willing to merge this stuff as long as we can label it as experimental

@jtarango
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jtarango commented Jul 2, 2020 via email

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3 participants