vregion: Cross core user-space DP fix - #11071
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August 6, 2026 20:31
The vregion metadata struct (containing the interim k_heap) is allocated from cached memory with rmalloc(0, ...). When a DP module on core 1 has its interim heap initialized during pipeline_complete, the k_heap data (including the sys_heap.heap pointer) is written to core 1's cache. If the IPC handler on core 0 later reads this data during a cross-core buffer bind, it gets stale/garbage values from main memory, causing a crash (EXCCAUSE 13: LoadStorePIFDataError) when the garbage pointer is dereferenced. Fix by allocating vregion metadata with SOF_MEM_FLAG_COHERENT so writes are immediately visible to all cores. Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
interim_heap_init() runs on one core (e.g. core 2 during pipeline_complete) and writes the k_heap/sys_heap/z_heap metadata to the vregion's page-allocated buffer. This buffer is in cached memory. When a different core (e.g. core 1) later tries to allocate from the interim heap, it reads stale data from its own cache, causing the allocation to fail despite sufficient space being available. Add sys_cache_data_flush_range() after k_heap_init() to flush the heap metadata to main memory so all cores see the initialized state. Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
jsarha
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August 7, 2026 09:56
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Pull request overview
Fixes cross-core user-space DP failures on PTL by addressing cache-coherency problems in vregion metadata and interim heap initialization so that heap state written on one core is visible/usable from other cores.
Changes:
- Allocate
struct vregionmetadata using coherent (uncached) memory to avoid cross-core stale cache visibility issues. - Flush interim heap backing memory after
k_heap_init()to reduce stale-cache exposure when another core starts allocating from the interim heap.
Comment on lines
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| /* Flush the heap metadata written by k_heap_init to main memory | ||
| * so other cores can access the interim heap without stale cache. | ||
| */ | ||
| sys_cache_data_flush_range(interim_base, interim_size); |
| /* Flush the heap metadata written by k_heap_init to main memory | ||
| * so other cores can access the interim heap without stale cache. | ||
| */ | ||
| sys_cache_data_flush_range(interim_base, interim_size); |
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I noticed some time ago that placing DP module to another core than the rest of the pipeline did not work on PTL any more. With other platforms it still worked and when turning CONFIG_USERSPACE=n PTL worked again too.
After some debugging I found out that there were some cache coherency issues in vregions that caused this. With these two fixes the sof-ptl-nocodec-dp-core-test.tplg topology works on PTL again too. I think we should add this or something similar to our CI. Maybe just edit nocodec topology a bit.