The Autonomous Sunk-Cost Fallacy: Stopping Failures and Meta-Reasoning in LLMs Deployed within the Autonomous Empirical Optimization System (AEOS)

Educational project that explores the AITL control architecture (PID × FSM × LLM) from Python modeling to ASIC implementation using Verilog, OpenLane, Magic, and ngspice.

Design Recovery Control is a control architecture that recovers control design assumptions under system degradation, using layered supervision of PID, FSM, and LLM.