Highspeed BASIC-52 V1.31 + I2C softcore running from internal 12kB ROM and 4kB RAM implemented inside MAX10 FPGA.
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Updated
Jul 12, 2025 - BASIC
Highspeed BASIC-52 V1.31 + I2C softcore running from internal 12kB ROM and 4kB RAM implemented inside MAX10 FPGA.
80C52 + 12kB ROM + 32kB RAM on Altera CYCLONE IV running with BASIC-52 +I2C on 12kB ROM
80C52 + 12kB ROM + 16kB RAM on Altera CYCLONE IV EP4CE6 running with BASIC-52 +I2C on 12kB ROM running at 50 MHz
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