A simple superscalar out-of-order RISC-V microprocessor
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Feb 24, 2025 - SystemVerilog
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computer-architecture
Here are 47 public repositories matching this topic...
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
fpga riscv heterogeneous-parallel-programming shared-memory computer-architecture openmp-parallelization many-core-architectures heterogeneous-computing iommu openmp-offloading unified-virtual-memory
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Sep 18, 2023 - SystemVerilog
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
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Dec 17, 2025 - SystemVerilog
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.
processor-architecture pipelines riscv vivado systemverilog computer-architecture gtkwave system-verilog university-course risc-v c-programming rv32i open-education verilator open-educational-resources processor-design assembly-programming hardware-software-codesign microcontroller-design
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Jun 5, 2025 - SystemVerilog
Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.
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Dec 15, 2025 - SystemVerilog
Minimalistic RV32I RISC-V Processor in System Verilog
fpga processor simulations systemverilog computer-architecture instruction-set-architecture risc-v digital-design rv32i
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Sep 19, 2023 - SystemVerilog
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Aug 5, 2023 - SystemVerilog
RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instruction set simulator and a random instruction generator in system verilog and a rudimetary assembler in python
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Jan 24, 2022 - SystemVerilog
Single-Cycle RISC-V Processor using SystemVerilog on a Nexys A7 (Artix-7) FPGA. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. It supports the complete RV32I instruction set (R, I, S, B, U, J types).
fpga vivado computer-architecture system-verilog risc-v cpu-architecture processor-design single-cycle-processor digital-design-and-computer-organization rv32i-processor
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Jul 21, 2025 - SystemVerilog
Arquitetura e Organização de Computadores usando RISC-V
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Nov 28, 2025 - SystemVerilog
Simple RISC-V Pipelined processor implemented on SystemVerilog.
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Jun 12, 2025 - SystemVerilog
A repository consisting of all the project files and codes for RISC-V Processor design using Transaction Level Verilog.
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Oct 3, 2023 - SystemVerilog
Micro-Programmed Multi-Cycle Processor
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Sep 9, 2020 - SystemVerilog
Impletations of Computer Architecture components and RISC-V CPU (SystemVerilog)
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Dec 19, 2023 - SystemVerilog
A 5-stage pipelined 64-bit ARM processor; implemented in SystemVerilog
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Nov 12, 2023 - SystemVerilog
A 5-Stage Pipelined RISC-V Processor designed and implemented on FPGA (Artix-7 Nexys A7). Supports RV32I instructions set (R, I, S, B, U, J types) with ALU, control unit, hazard detection, forwarding, and pipeline registers. Verified through simulation and hardware testing with optimized timing and 4× performance gain.
fpga processor systemverilog pipelining computer-architecture hazard-detection risc-v system-design riscv32 datapath-design pipelined-processor control-logic
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Oct 13, 2025 - SystemVerilog
Single & Multi-cycle implementation of a subset of RISC-V for educational purposes.
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Oct 10, 2025 - SystemVerilog
5 stages RISC pipelined processor with multiple instructions implemented in verilog including ALU Operations, Interrupts as a state machine, Jumps and branching instructions, Memory operations and more.. following Harvard architecture.
memory assembler verilog systemverilog computer-architecture interrupts hazards pipelined-processors alu-digital-circuit
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Jan 7, 2023 - SystemVerilog
Self-directed design of a two-level cache hierarchy. Completed over winter break following fall 2024.
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Jan 12, 2025 - SystemVerilog
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