Solution to COA LAB Assgn, IIT Kharagpur

An Implementation of MIPS processor with single cycle architecture using Verilog.

A collection of practical sessions exploring FPGA programming and MIPS-based systems using the ALTERA Cyclone V DE-1 SoC board.

Implementation of a MIPS CPU using Verilog.

An implementation of 32-bits MIPS Single Cycle Datapath in Verilog HDL.

Full FPGA Implementation of 32-bit FSM-based Multi-State MIPS Processor

Computer Organization and Design (2nd year - 3rd semester)

Verilog Description for a 32bit MIPS Processor

Sngle-cycle, Multi-cycle and Pipeline MIPS implementations; Spring 2022

Verilog descriptions of MIPS single-cycle, multi-cycle & pipeline implementations.

This is NSU CSE332 course's project that starts with learning about ISA, assembly language, advanced ALU, data path and control, pipelining in theory.

BitStreamOS --- A custom-designed MIPS CPU and operating system built from scratch. Features include a custom instruction set, assembler for converting assembly code to binary, CPU simulation with test benches, waveform visualization, and a basic OS implementation.

Course project for Computer Design and Practice at HIT.

This is a single cycle processor, which processes each instruction in single clock cycle, working on Instruction Set Architecture (ISA) specified in the documentation.

This is a functioning MIPS CPU designed in Verilog to run an an xilinx fpga.

Computer Organization

Verilog / MIPS / assembly projects

Implementation of MIPS Processor Modules Using Verilog

Projeto em FPGA com processador MIPS e SO simples, desenvolvido em disciplinas da UNIFESP-SJC. / FPGA project with MIPS processor and simple OS, developed in UNIFESP-SJC courses.