Gatorom TMS320C28x Decoder Format

[edgetriggered]

This is a sub-issue for #62 resolved by adding a decoder module and unit test for Texas Instruments' TMS320C28x family of digital signal processors, not currently supported by Zorrom.

[travisgoodspeed]

Thanks for the PR! Could you describe a bit about the layout and how things might change as the ROM size changes?

[edgetriggered]

Duplicated from PR #131:

ROM banks in this part family consist of rows of 1024 bits comprising four meta-columns, each containing sixteen sub-columns. Words are composed of bits from the same position in each sub-column, advancing to the next meta-column for the next word. After four words, the process continues from the next sub-column position and resets when advancing to the next row once all sub-column positions in the row are exhausted.

Python-style slices to help establish the pattern:

Word 0: row[0][0+0:256:16]
Word 1: row[0][0+256:512:16]
Word 2: row[0][0+512:768:16]
Word 3: row[0][0+768:1024:16]
Word 4: row[0][1+0:256:16]
Word 5: row[0][1+256:512:16]
Word 6: row[0][1+512:768:16]
Word 7: row[0][1+768:1024:16]
Word 8: row[0][2+0:256:16]
...
Word 64: row[1][0:256:16]
...

The module as-is has strict requirements about the ROM layout, including 16-bit word size and exactly 1024 bits in each row. It works, but this could likely be generalized for ROMs in other part families using a similar layout. This appears to be a "packed" variant of cols-{left,right} where multiple words are interleaved from the same position and it may be possible to incorporate this functionality into those modules without negatively affecting other targets. For example, it may be a valid assumption to treat all ROMs of a width greater than wordsize×wordsize as this variation.