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example: add example demonstrating an ASK modulator (#28)
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‎examples/ask_modulator/README.md‎

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# Shrike-Lite ASK Modulator
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This project implements a mixed-signal Digital-to-Analog communication system using the Shrike-Lite board. It leverages the RP2040 as a Control Plane (Data/Protocol) and the ForgeFPGA as a Data Plane (Direct Digital Synthesis & PWM).
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The system generates a smooth Sine Wave using DDS (Direct Digital Synthesis), converts it to a digital bitstream using PWM, and modulates it using Amplitude Shift Keying (ASK) commands from the RP2040.
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To understand the working principle of DDS and PWM audio generation, refer to:
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[FPGA DDS Tutorial](https://www.fpga4fun.com/DDS.html).
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---
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## Block Diagram
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```mermaid
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graph LR
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A[RP2040 MCU] -- 6-Bit Frequency Bus --> B[FPGA Input GPIO]
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A -- Data/Enable Signal --> B
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B -- Tuning Word --> C[DDS Logic]
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C -- Sine Value --> D[PWM Generator]
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D -- Digital Pulses --> E[FPGA Output Pin]
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E -- RC Filter --> F[Analog Scope/Audio]
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```
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## Overview on FPGA Side
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The FPGA logic (`dds_ask_modulator`) acts as a high-speed synthesizer consisting of three main stages:
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1. **Phase Accumulator:** A 16-bit counter that increments by a specific "Tuning Word" value every clock cycle. The speed of the overflow determines the carrier frequency.
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2. **Sine Look-Up Table (LUT):** A 64-entry ROM that maps the phase value to a digital amplitude (0 to 63), creating a sine wave shape.
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3. **PWM Generator:** Converts the 6-bit amplitude into a 1-bit high-speed Pulse Width Modulated signal (approx 780 kHz switching rate) suitable for RC filtering.
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The modulation is performed logically at the output stage:
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- If `i_data` is High: The generated Sine Wave is passed to the output.
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- If `i_data` is Low: The output is forced to 0 (Silence).
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---
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## Features
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- **Direct Digital Synthesis (DDS):** Generates mathematically precise sine waves without external DAC chips.
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- **Hybrid Architecture:** Offloads fast signal generation (50 MHz logic) to FPGA, keeping the MCU free for text processing and timing.
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- **Configurable Carrier:** A 6-bit parallel bus allows the RP2040 to tune the carrier frequency instantly.
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- **ASK (Amplitude Shift Keying):** Implements On-Off Keying (OOK) to transmit binary data bursts.
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- **Custom Encoding:** Implements a custom 6-bit character map for alphanumeric transmission over the ASK link.
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---
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## Top Module Interface
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| Signal | Direction | Description |
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| :--- | :--- | :--- |
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| `i_clk` | In | System clock (50 MHz Internal Oscillator) |
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| `i_freq_word[5:0]` | In | 6-Bit Tuning Word (Controls Carrier Pitch) |
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| `i_data` | In | Modulation Signal (1=Carrier ON, 0=Silence) |
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| `o_pwm_out` | Out | PWM Digital Output (Requires Filter) |
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| `o_pwm_out_oe` | Out | Output Enable (Always 1) |
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| `o_clk_en` | Out | Oscillator Enable (Always 1) |
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---
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## Parameters & Math
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#### `CLK_FREQ :`
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- System clock frequency.
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- `50 MHz`
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#### `PWM CARRIER :`
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- The PWM switching frequency is derived from the clock and the resolution ($2^6$).
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- `50 MHz / 64 steps ≈ 781.25 kHz`
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#### `OUTPUT FREQUENCY :`
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- The audible output frequency is determined by the Tuning Word ($TW$) sent by the RP2040.
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- $F_{out} = \frac{F_{clk} \times TW}{2^{16}}$
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- With $TW=1$, Output $\approx 762 \text{ Hz}$ (Optimal for filtering).
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---
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## Hardware Setup
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### 1. The RC Filter (Demodulator)
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The FPGA output is a digital square wave. To see the sine wave on an oscilloscope, an RC Low Pass Filter is required to reconstruct the analog signal.
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* **Resistor:** 1 kΩ
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* **Capacitor:** 10 nF (Code 103) - *Cutoff ~15.9 kHz*
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* **Connection:** Connect Resistor to FPGA Output. Connect Capacitor from Resistor leg to Ground. Probe the junction between R and C.
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### 2. Pin Interconnects (Jumper Wires)
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Due to pin availability on the specific package, a mixed-header wiring scheme is used. Ensure **Common Ground** between headers.
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| Signal | RP2040 Pin | FPGA Pin (Board Label) | Physical Pin (Bitstream) |
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| :--- | :--- | :--- | :--- |
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| **Freq Bit 0 (LSB)** | **GPIO 5** | **FPGA_IO1** | **PIN 14** |
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| **Freq Bit 1** | **GPIO 6** | **FPGA_IO2** | **PIN 15** |
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| **Freq Bit 2** | **GPIO 7** | **FPGA_IO17** | **PIN 8** |
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| **Freq Bit 3** | **GPIO 8** | **FPGA_IO18** | **PIN 9** |
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| **Freq Bit 4** | **GPIO 9** | **FPGA_IO8** | **PIN 23** |
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| **Freq Bit 5 (MSB)** | **GPIO 10**| **FPGA_IO9** | **PIN 24** |
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| **Data / Enable** | **GPIO 16**| **FPGA_IO0** | **PIN 13** |
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| **Power Control** | **GPIO 12/13** | *(Internal)* | *(Internal)* |
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| **PWM Output** | *(None)* | **FPGA_IO14** | **PIN 5** |
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> **Note:** FPGA Physical Pins refer to the IO Manager mapping in Go Configure.
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---
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## Firmware Overview
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The control logic is written in **MicroPython** running on the RP2040.
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1. **`flash.py`:** Uses the `shrike` library to write the Verilog bitstream (`.bin`) from the RP2040 filesystem into the FPGA configuration memory.
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2. **`main.py`:**
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* Initializes the 6-bit Parallel Bus to set the Carrier Frequency.
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* Powers up the FPGA Core (GPIO 12) and IOs (GPIO 13).
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* Implements a **Custom 6-Bit Look-Up Table** to map characters (A-Z, 0-9) to specific 6-bit integer codes.
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* Transmits the string `"HelloShrike123"` by toggling the `i_data` pin (ASK) using a Start-Bit/Stop-Bit protocol.
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### Exercise for the User
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The current implementation utilizes a custom, optimized 6-bit codebook to map alphanumeric characters to the available bandwidth.
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**A full standard ASCII (8-bit) implementation requires splitting characters into two 4-bit nibbles or serializing the data further. This implementation is left as an exercise for the reader.**
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---
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## Quick Steps
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1. **Synthesize:** Generate the bitstream in Go Configure with the pin map above.
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2. **Upload:** Copy `FPGA_bitstream_MCU.bin`, `flash.py`, and `helloshrike.py` to the RP2040 via Thonny/VS Code.
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3. **Flash:** Run `flash.py` once to configure the FPGA.
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4. **Run:** Run `helloshrike.py` to start the transmission loop.
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5. **Observe:** Connect Oscilloscope to **FPGA_IO14**. Set Timebase to `50ms/div` and Trigger to `Normal`.
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## Expected Output
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When running `helloshrike.py`, the oscilloscope will show bursts of Sine Waves corresponding to the logic levels of the transmitted text:
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* **Logic 1:** 3V Sine Wave (Carrier ON)
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* **Logic 0:** 0V Flat Line (Carrier OFF)
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Output on the terminal should look like as shown below:
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```
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--- Transmitting: HelloShrike123 ---
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Sending 'H' -> Code 01 -> 000001
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Sending 'e' -> Code 02 -> 000010
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Sending 'l' -> Code 03 -> 000011
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Sending 'l' -> Code 03 -> 000011
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Sending 'o' -> Code 04 -> 000100
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Sending 'S' -> Code 05 -> 000101
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Sending 'h' -> Code 06 -> 000110
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Sending 'r' -> Code 07 -> 000111
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Sending 'i' -> Code 08 -> 001000
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Sending 'k' -> Code 09 -> 001001
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Sending 'e' -> Code 02 -> 000010
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Sending '1' -> Code 51 -> 110011
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Sending '2' -> Code 52 -> 110100
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Sending '3' -> Code 53 -> 110101
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```
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The signal will look like a structured sequence of bursts separated by silence, representing the binary data of the text string.

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