invalid vector codegen with riscv64

[andrewrk]

Test [197/1295] fmt.test "std-riscv64-linux-none-Debug-bare-multi vector"...
====== expected this output: =========
{ true, false, true, false }
======== instead found this: =========
{ true, true, true, true }
======================================

To reproduce:

In the llvm10 branch, remove this:

zig/lib/std/fmt.zig

Lines 1735 to 1738 in 64365bc

	if (builtin.arch == .riscv64) {
	// https://github.com/ziglang/zig/issues/4486
	return error.SkipZigTest;
	}

Additionally grep for that URL / issue number and make sure no other test skips exist. Next:

./zig test ../lib/std/std.zig -target riscv64-linux

Related: #3317

cc @luismarques

[lunagl]

This seems to be fixed in LLVM. I haven't found the relevant issue/commit, but the test passes for me with LLVM 20.1.6.
Should I make a PR enabling it again?

[alexrp]

Please wait for #25055 to be merged first, then yes.