Sub-board infrastructure with export-tap

compiler/src/main/scala/edg/ElemBuilder.scala

@@ -44,23 +44,27 @@ object ElemBuilder {
     def Exported(
         external: ref.LocalPath,
         internal: ref.LocalPath,
-        expanded: Seq[expr.ValueExpr] = Seq()
+        expanded: Seq[expr.ValueExpr] = Seq(),
+        tap: Boolean = false
     ): expr.ValueExpr = expr.ValueExpr(
       expr = expr.ValueExpr.Expr.Exported(expr.ExportedExpr(
         exteriorPort = Some(ValueExpr.Ref(external)),
         internalBlockPort = Some(ValueExpr.Ref(internal)),
-        expanded = expanded.map(_.getExported)
+        expanded = expanded.map(_.getExported),
+        tap = tap
       ))
     )
     def ExportedArray(
         external: ref.LocalPath,
         internal: ref.LocalPath,
-        expanded: Seq[expr.ValueExpr] = Seq()
+        expanded: Seq[expr.ValueExpr] = Seq(),
+        tap: Boolean = false
     ): expr.ValueExpr = expr.ValueExpr(
       expr = expr.ValueExpr.Expr.ExportedArray(expr.ExportedExpr(
         exteriorPort = Some(ValueExpr.Ref(external)),
         internalBlockPort = Some(ValueExpr.Ref(internal)),
-        expanded = expanded.map(_.getExported)
+        expanded = expanded.map(_.getExported),
+        tap = tap
       ))
     )
     // variation for map_extract

compiler/src/main/scala/edg/compiler/Compiler.scala

@@ -37,7 +37,7 @@ object ElaborateRecord {
   // Connection to be elaborated, to set port parameter, IS_CONNECTED, and CONNECTED_LINK equivalences.
   // Only elaborates the direct connect, and for bundles, creates sub-Connect tasks since it needs
   // connectedLink and linkParams.
-  case class Connect(toLinkPortPath: DesignPath, toBlockPortPath: DesignPath, root: DesignPath)
+  case class Connect(toLinkPortPath: DesignPath, toBlockPortPath: DesignPath, root: DesignPath, tap: Boolean = false)
       extends ElaborateTask
 
   // Elaborates the contents of a port array, based on the port array's ELEMENTS parameter.
@@ -117,7 +117,7 @@ class AssignNamer() {
 }
 
 object Compiler {
-  final val kExpectedProtoVersion = 11
+  final val kExpectedProtoVersion = 12
 }
 
 /** Compiler for a particular design, with an associated library to elaborate references from.
@@ -279,12 +279,14 @@ class Compiler private (
     val toLinkPort = resolvePort(connect.toLinkPortPath).asInstanceOf[wir.HasParams]
     val connectedParam = toLinkPort.getParams.keys.map(IndirectStep.Element(_))
     for (connectedStep <- connectedParam) { // note: can't happen for top level connect!
-      constProp.addAssignEqual(
-        connect.toLinkPortPath.asIndirect + connectedStep,
-        connect.toBlockPortPath.asIndirect + connectedStep,
-        connect.root,
-        "connect"
-      )
+      if (!connect.tap) { // tap is non-propagating
+        constProp.addAssignEqual(
+          connect.toLinkPortPath.asIndirect + connectedStep,
+          connect.toBlockPortPath.asIndirect + connectedStep,
+          connect.root,
+          "connect"
+        )
+      }
     }
 
     // Add sub-ports to the elaboration dependency graph, as appropriate
@@ -295,7 +297,8 @@ class Compiler private (
             ElaborateRecord.Connect(
               connect.toLinkPortPath + portName,
               connect.toBlockPortPath + portName,
-              connect.root
+              connect.root,
+              connect.tap
             ),
             Seq()
           )
@@ -499,11 +502,12 @@ class Compiler private (
           case (ValueExpr.Ref(extPort), ValueExpr.Ref(intPort)) =>
             if (!isInLink) {
               elaboratePending.addNode(
-                ElaborateRecord.Connect(blockPath ++ extPort, blockPath ++ intPort, blockPath),
+                ElaborateRecord.Connect(blockPath ++ extPort, blockPath ++ intPort, blockPath, tap = exported.tap),
                 Seq(ElaborateRecord.Port(blockPath ++ extPort))
               )
               constProp.setConnection(blockPath ++ extPort, blockPath ++ intPort)
             } else { // for links, the internal port is towards the inner link, so the args are flipped
+              require(!exported.tap, "tap not allowed in links")
               elaboratePending.addNode(
                 ElaborateRecord.Connect(blockPath ++ intPort, blockPath ++ extPort, blockPath),
                 Seq(ElaborateRecord.Port(blockPath ++ intPort))
@@ -514,6 +518,7 @@ class Compiler private (
           case _ => false // anything with allocates is not processed
         }
       case expr.ValueExpr.Expr.ExportedTunnel(exported) =>
+        require(!exported.tap, "tap not allowed in tunnel")
         (exported.getExteriorPort, exported.getInternalBlockPort) match {
           case (ValueExpr.Ref(extPort), ValueExpr.Ref(intPort)) =>
             require(!isInLink)
@@ -845,12 +850,14 @@ class Compiler private (
 
                     case expr.ValueExpr.Expr.ExportedArray(exported) => // note internal port is portPostfix
                       val ValueExpr.Ref(extPostfix) = exported.getExteriorPort
-                      constProp.addAssignEqual(
-                        path.asIndirect ++ extPostfix + IndirectStep.Elements,
-                        path.asIndirect ++ portPostfix + IndirectStep.Elements,
-                        path,
-                        constrName
-                      )
+                      if (!exported.tap) { // elements do not propagate in tap case, but are checked to be equal
+                        constProp.addAssignEqual(
+                          path.asIndirect ++ extPostfix + IndirectStep.Elements,
+                          path.asIndirect ++ portPostfix + IndirectStep.Elements,
+                          path,
+                          constrName
+                        )
+                      }
                       constProp.addAssignEqual(
                         path.asIndirect ++ portPostfix + IndirectStep.Allocated,
                         path.asIndirect ++ extPostfix + IndirectStep.Allocated,

compiler/src/main/scala/edg/compiler/ExportTapCheck.scala

@@ -0,0 +1,109 @@
+package edg.compiler
+
+import edg.ExprBuilder.ValueExpr
+import edg.wir.{DesignPath, IndirectStep}
+import edg.wir.ProtoUtil.{ConstraintProtoToSeqMap, ParamProtoToSeqMap}
+import edgir.elem.elem
+import edgir.expr.expr
+import edgir.ref.ref
+
+import scala.collection.SeqMap
+import scala.collection.mutable
+
+/** Checks export tap validity, that inner-side parameters are undefined and elements are consistent.
+  */
+class ExportTapCheck(compiler: Compiler)
+    extends DesignMap[Unit, Seq[CompilerError], Unit] {
+  val portParams = mutable.HashMap[DesignPath, Seq[String]]()
+
+  def mapExported(
+      containingPath: DesignPath,
+      exportName: String,
+      exported: expr.ExportedExpr
+  ): Seq[CompilerError] = {
+    val (ValueExpr.Ref(extPort), ValueExpr.Ref(intPort)) = (exported.getExteriorPort, exported.getInternalBlockPort)
+    portParams(containingPath ++ extPort).flatMap { paramName =>
+      val paramPath = containingPath.asIndirect ++ intPort + paramName
+      val exportedErrors = compiler.getValue(paramPath) match {
+        case Some(_) => Seq(CompilerError.ExprError(
+            paramPath,
+            "export tap internal port parameter must be undefined"
+          ))
+        case None => Seq()
+      }
+      exportedErrors ++ exported.expanded.flatMap(expr =>
+        mapExported(containingPath, exportName, expr)
+      )
+    }
+  }
+
+  def mapConstraint(
+      containingPath: DesignPath,
+      constrName: String,
+      constr: expr.ValueExpr
+  ): Seq[CompilerError] = {
+    constr.expr match {
+      case expr.ValueExpr.Expr.Exported(exported) if exported.tap =>
+        mapExported(containingPath, constrName, exported)
+      case expr.ValueExpr.Expr.ExportedArray(exported) if exported.tap =>
+        val (ValueExpr.Ref(extPort), ValueExpr.Ref(intPort)) = (exported.getExteriorPort, exported.getInternalBlockPort)
+        val exportedArrayContainerErrors =
+          if (
+            compiler.getValue(containingPath.asIndirect ++ extPort + IndirectStep.Elements) == compiler.getValue(
+              containingPath.asIndirect ++ intPort + IndirectStep.Elements
+            )
+          ) {
+            Seq()
+          } else {
+            Seq(CompilerError.ExprError(
+              containingPath.asIndirect + constrName,
+              "inconsistent export tap array port elements"
+            ))
+          }
+        exportedArrayContainerErrors ++ mapExported(containingPath, constrName, exported)
+      case _ => Seq() // other constructs ignored
+    }
+  }
+
+  override def mapPort(path: DesignPath, port: elem.Port, ports: SeqMap[String, Unit]): Unit = {
+    portParams.put(path, port.params.asPairs.map { case (name, _) => name }.toSeq)
+  }
+  override def mapPortArray(path: DesignPath, port: elem.PortArray, ports: SeqMap[String, Unit]): Unit = {
+    portParams.put(path, Seq())
+  }
+  override def mapPortLibrary(path: DesignPath, port: ref.LibraryPath): Unit = {}
+
+  override def mapBlock(
+      path: DesignPath,
+      block: elem.HierarchyBlock,
+      ports: SeqMap[String, Unit],
+      blocks: SeqMap[String, Seq[CompilerError]],
+      links: SeqMap[String, Unit]
+  ): Seq[CompilerError] = {
+    block.constraints.asPairs.flatMap {
+      case (name, constr) => mapConstraint(path, name, constr)
+    }.toSeq ++ blocks.values.flatten
+  }
+  override def mapBlockLibrary(path: DesignPath, block: ref.LibraryPath): Seq[CompilerError] = {
+    Seq() // block library errors should be checked elsewhere
+  }
+
+  override def mapLink(
+      path: DesignPath,
+      link: elem.Link,
+      ports: SeqMap[String, Unit],
+      links: SeqMap[String, Unit]
+  ): Unit = {} // export tap not valid in links
+
+  override def mapLinkArray(
+      path: DesignPath,
+      link: elem.LinkArray,
+      ports: SeqMap[String, Unit],
+      links: SeqMap[String, Unit]
+  ): Unit = {} // export tap not valid in links
+
+  override def mapLinkLibrary(
+      path: DesignPath,
+      link: ref.LibraryPath
+  ): Unit = {} // link library errors should be checked elsewhere
+}

compiler/src/main/scala/edg/compiler/ExprToString.scala

@@ -191,7 +191,11 @@ class ExprToString() extends ValueExprMap[String] {
       expandedExteriorPort: String,
       expandedInterorPort: String
   ): String = {
-    s"exported($exteriorPort, $internalBlockPort)"
+    if (!exported.tap) {
+      s"exported($exteriorPort, $internalBlockPort)"
+    } else {
+      s"exported[tap]($exteriorPort, $internalBlockPort)"
+    }
   }
 
   override def mapExportedTunnel(