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[TRTLLM-11057][feat] Add Helix CP support for DSV3.2 - #11507

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brb-nv:user/brb/helix-for-dsv3.2
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[TRTLLM-11057][feat] Add Helix CP support for DSV3.2#11507
brb-nv merged 4 commits into
NVIDIA:mainfrom
brb-nv:user/brb/helix-for-dsv3.2

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@brb-nv brb-nv commented Feb 13, 2026

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Description

This MR adds Helix support for DSV3.2. Also cherry-picks below MR from release branch to unblock this MR:
#11252

Test Coverage

$ pytest tests/integration/defs/accuracy/test_disaggregated_serving.py::TestDeepSeekV32Exp::test_auto_dtype_with_helix -s -v
$ TRTLLM_USE_UCX_KVCACHE=1 TLLM_LOG_LEVEL=INFO mpirun -n 8 ./tests/unit_tests/multi_gpu/cacheTransceiverTest --gtest_filter="AsymmetricCaseTest*WithCPForMLA/AsymmetricalCacheTest.TestCase/*"
$ TRTLLM_USE_UCX_KVCACHE=1 TLLM_LOG_LEVEL=INFO mpirun -n 8 ./tests/unit_tests/multi_gpu/cacheTransceiverTest --gtest_filter="AsymmetricCaseTestWithCPAndDPForMLA*/AsymmetricalCacheTestWithDP.TestCase/*"
$ TRTLLM_USE_UCX_KVCACHE=1 TLLM_LOG_LEVEL=INFO mpirun -n 8 ./tests/unit_tests/multi_gpu/cacheTransceiverTest --gtest_filter="AsymmetricCaseTest*WithCPForMLAUnevenLayer/AsymmetricalCacheTest.TestCase/*"

PR Checklist

Please review the following before submitting your PR:

  • PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.

  • PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.

  • Test cases are provided for new code paths (see test instructions)

  • Any new dependencies have been scanned for license and vulnerabilities

  • CODEOWNERS updated if ownership changes

  • Documentation updated as needed

  • Update tava architecture diagram if there is a significant design change in PR.

  • The reviewers assigned automatically/manually are appropriate for the PR.

  • Please check this after reviewing the above items as appropriate for this PR.

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Summary by CodeRabbit

Release Notes

  • Bug Fixes

    • Fixed cache indexing logic for KV cache distribution across parallel ranks.
    • Improved cache metadata propagation for accurate block initialization.
  • New Features

    • Added Helix context parallelism support for attention operations.
    • Enhanced sequence length optimization for context parallel configurations.
  • Tests

    • Expanded accuracy testing for Helix-based distributed serving.
    • Added comprehensive test coverage for new model variants.

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brb-nv requested review from a team as code owners February 13, 2026 08:08
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brb-nv requested review from 2ez4bz, hlu1 and yuxianq February 13, 2026 08:08
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brb-nv force-pushed the user/brb/helix-for-dsv3.2 branch from 809cbfa to cd68c05 Compare February 13, 2026 08:10
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📝 Walkthrough

Walkthrough

This PR introduces Context Parallel (CP) support for Helix-based distributed serving, including CP-major cache indexing for MLA KV caches, CP-aware reduction logic in DeepSeekV3 attention modules, Helix-specific sequence length scaling, and corresponding test coverage expansion with new Helix-based evaluation paths.

Changes

Cohort / File(s) Summary
CP-Major Cache Indexing
cpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp, cpp/tests/unit_tests/multi_gpu/cacheTransceiverTest.cpp
Updated MLA KV cache indexing to use CP-major ordering by deriving CP and PP domain indices from process index, computing cacheIdx as cpDomainIdx \* pPDomainSize + ppDomainIdx. Enhanced test with CP metadata propagation for indexer block initialization using global block IDs.
Helix CP Sequence Length Handling
tensorrt_llm/_torch/attention_backend/sparse/dsa.py, tensorrt_llm/_torch/pyexecutor/model_engine.py
Modified KV lens computation to distinguish between active and inactive ranks when Helix CP is enabled, and scaled effective_max_seq_len by cp_size to ensure position IDs stay within RoPE limits during CUDA graph warmup.
CP-Aware DeepSeekV3 Attention
tensorrt_llm/_torch/models/modeling_deepseekv3.py
Added optional mapping_with_cp parameter to DeepseekV32Attention and DeepseekV3DecoderLayer, introducing dynamic CP/TP reduction logic via needs_cp_reduce and needs_tp_reduce flags to replace static reduction behavior.
Helix Integration Tests
tests/integration/defs/accuracy/test_disaggregated_serving.py, tests/integration/test_lists/qa/llm_function_core.txt, tests/integration/test_lists/test-db/l0_dgx_b200.yml
Added test_auto_dtype_with_helix parameterized test method with multiple CP/TP/PP/MOE configurations and backend variants (nccl/fifo with/without CUDA graphs); extended test coverage for DeepSeekV32Exp with Helix parallelism; swapped execution backends in test database from nccl-cudagraph to fifo-cudagraph for DeepSeek variants.

Estimated code review effort

🎯 3 (Moderate) | ⏱️ ~22 minutes

Possibly related PRs

  • #10350: Modifies cache/rank indexing in mlaCacheFormatter.cpp to use CP-major ordering for decomposing process indices into CP and TP/PP domains, directly related to the same indexing rework.

Suggested reviewers

  • schetlur-nv
  • chuangz0
  • yuxianq
🚥 Pre-merge checks | ✅ 1 | ❌ 3

❌ Failed checks (2 warnings, 1 inconclusive)

Check name Status Explanation Resolution
Docstring Coverage ⚠️ Warning Docstring coverage is 11.11% which is insufficient. The required threshold is 80.00%. Write docstrings for the functions missing them to satisfy the coverage threshold.
Merge Conflict Detection ⚠️ Warning ❌ Merge conflicts detected (24 files):

⚔️ cpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp (content)
⚔️ cpp/tests/unit_tests/multi_gpu/cacheTransceiverTest.cpp (content)
⚔️ tensorrt_llm/_torch/attention_backend/sparse/dsa.py (content)
⚔️ tensorrt_llm/_torch/auto_deploy/transform/library/ssm_cache.py (content)
⚔️ tensorrt_llm/_torch/models/modeling_deepseekv3.py (content)
⚔️ tensorrt_llm/_torch/modules/fused_moe/communication/communication_factory.py (content)
⚔️ tensorrt_llm/_torch/modules/fused_moe/communication/deep_ep.py (content)
⚔️ tensorrt_llm/_torch/modules/fused_moe/communication/deep_ep_low_latency.py (content)
⚔️ tensorrt_llm/_torch/modules/fused_moe/configurable_moe.py (content)
⚔️ tensorrt_llm/_torch/modules/fused_moe/fused_moe_cute_dsl.py (content)
⚔️ tensorrt_llm/_torch/modules/fused_moe/fused_moe_cutlass.py (content)
⚔️ tensorrt_llm/_torch/modules/fused_moe/fused_moe_deepgemm.py (content)
⚔️ tensorrt_llm/_torch/modules/fused_moe/fused_moe_triton.py (content)
⚔️ tensorrt_llm/_torch/modules/fused_moe/fused_moe_trtllm_gen.py (content)
⚔️ tensorrt_llm/_torch/modules/fused_moe/interface.py (content)
⚔️ tensorrt_llm/_torch/modules/fused_moe/quantization.py (content)
⚔️ tensorrt_llm/_torch/pyexecutor/model_engine.py (content)
⚔️ tests/integration/defs/accuracy/test_disaggregated_serving.py (content)
⚔️ tests/integration/test_lists/qa/llm_function_core.txt (content)
⚔️ tests/integration/test_lists/test-db/l0_dgx_b200.yml (content)
⚔️ tests/integration/test_lists/waives.txt (content)
⚔️ tests/unittest/_torch/modules/moe/quantize_utils.py (content)
⚔️ tests/unittest/_torch/modules/moe/test_moe_backend.py (content)
⚔️ tests/unittest/_torch/modules/moe/test_moe_module.py (content)

These conflicts must be resolved before merging into main.
Resolve conflicts locally and push changes to this branch.
Description check ❓ Inconclusive PR description includes title, summary of changes, test coverage commands, and completed checklist, but lacks detailed explanation of what Helix CP support entails and why this change is needed. Enhance the Description section to explain: (1) what Helix CP (control-plane) support means, (2) why it's needed for DSV3.2, (3) specific technical changes being made, and (4) clarify the cherry-picked PR 11252 dependency.
✅ Passed checks (1 passed)
Check name Status Explanation
Title check ✅ Passed The title clearly and specifically summarizes the main change: adding Helix control-plane (CP) support for DeepSeek V3.2 (DSV3.2), which aligns with the core changes across multiple files including cache formatting, attention mechanisms, and integration tests.

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Actionable comments posted: 2

Caution

Some comments are outside the diff and can’t be posted inline due to platform limitations.

⚠️ Outside diff range comments (4)
tensorrt_llm/_torch/attention_backend/sparse/dsa.py (1)

1-3: ⚠️ Potential issue | 🟠 Major

Add required NVIDIA copyright header for this modified Python file.

This file is modified in this PR but does not include the mandated NVIDIA Apache‑2.0 header with the latest modification year (2026). Please add/update the header at the top.

As per coding guidelines: "All source files must contain an NVIDIA copyright header with the year of latest meaningful modification. Use the Apache License 2.0 format. Include NVIDIA copyright header on ALL new files and update year on modified files."

tests/integration/defs/accuracy/test_disaggregated_serving.py (1)

1-3: ⚠️ Potential issue | 🟠 Major

Add required NVIDIA copyright header for this modified Python file.

This file is modified in this PR but does not include the mandated NVIDIA Apache‑2.0 header with the latest modification year (2026). Please add/update the header at the top.

As per coding guidelines: "All source files must contain an NVIDIA copyright header with the year of latest meaningful modification. Use the Apache License 2.0 format. Include NVIDIA copyright header on ALL new files and update year on modified files."

cpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp (1)

1-3: ⚠️ Potential issue | 🟠 Major

Update NVIDIA copyright year to 2026.

This file is modified in this PR; update the header year to reflect the latest meaningful modification.

As per coding guidelines: "All source files must contain an NVIDIA copyright header with the year of latest meaningful modification. Use the Apache License 2.0 format. Include NVIDIA copyright header on ALL new files and update year on modified files."

cpp/tests/unit_tests/multi_gpu/cacheTransceiverTest.cpp (1)

2-2: ⚠️ Potential issue | 🟡 Minor

Copyright year needs updating to 2026.

The file has been meaningfully modified in 2026, but the copyright header still reads 2023-2025. As per coding guidelines, all source files must contain an NVIDIA copyright header with the year of latest meaningful modification.

- * SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2023-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
🤖 Fix all issues with AI agents
In `@cpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp`:
- Around line 256-270: The local index variables in the sendBufferFun lambda
(cpDomainIdx, ppDomainIdx, cacheIdx) are computed once and never modified;
update their declarations to be const to follow the coding guideline that
non-mutated variables be const—modify the lambda inside sendBufferFun to declare
cpDomainIdx, ppDomainIdx and cacheIdx as const (using the existing expressions
involving processIdx, connectionsPerCPDomain and pPDomainSize) so behavior is
unchanged but the variables are immutable.
- Around line 252-270: The code assumes connections.size() is divisible by
cPDomainSize when computing connectionsPerCPDomain; add explicit validation in
the scope where connectionsPerCPDomain is computed (before the lambda that
defines sendBufferFun) to check divisibility and non-zero cPDomainSize, e.g.,
ensure cPDomainSize > 0 and connections.size() % cPDomainSize == 0, and also
validate that the computed cacheIdx (using cpDomainIdx = processIdx /
connectionsPerCPDomain and ppDomainIdx = (processIdx % connectionsPerCPDomain) %
pPDomainSize) will be < outputSplitCaches.size() for all processIdx values; if
any check fails, return or throw an error (or log via TLLM_CHECK_WITH_INFO) to
prevent out‑of‑range access in sendBufferFun.
🧹 Nitpick comments (1)
cpp/tests/unit_tests/multi_gpu/cacheTransceiverTest.cpp (1)

1911-1966: Missing inline parameter comments for the last three test parameters.

The new UnevenLayer test instantiations omit the /*isIndexerKCache*/, /*indexerDimPerHead*/, and /*indexerKCacheQuantBlockSize*/ inline comments on their final arguments (e.g., line 1928, 1947, 1966), unlike the nearby CP test instantiations (e.g., lines 1841–1843, 1863–1865) which include these comments. Adding them improves readability and consistency.

Comment thread cpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp
Comment thread cpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp

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Approving changes to tensorrt_llm/_torch/models, with a small clarification question.

Comment thread tensorrt_llm/_torch/models/modeling_deepseekv3.py
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/bot run --disable-fail-fast

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PR_Github #36106 [ run ] triggered by Bot. Commit: 2fa7c3c

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PR_Github #36106 [ run ] completed with state FAILURE. Commit: 2fa7c3c
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/bot run --disable-fail-fast

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PR_Github #36179 [ run ] triggered by Bot. Commit: 2fa7c3c Link to invocation

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PR_Github #36179 [ run ] completed with state FAILURE. Commit: 2fa7c3c
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@brb-nv brb-nv changed the title [None][feat] Add Helix CP support for DSV3.2 [TRTLLM-11057][feat] Add Helix CP support for DSV3.2 Feb 19, 2026
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/bot run --disable-fail-fast

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PR_Github #36197 [ run ] triggered by Bot. Commit: 2fa7c3c Link to invocation

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PR_Github #36201 [ run ] triggered by Bot. Commit: 7a42fa1 Link to invocation

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/bot run --only-multi-gpu-test --disable-fail-fast

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/bot run --only-multi-gpu-test --disable-fail-fast

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PR_Github #37911 [ run ] triggered by Bot. Commit: 307379c Link to invocation

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/bot run --only-multi-gpu-test --disable-fail-fast

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PR_Github #37917 [ run ] triggered by Bot. Commit: ba5c970 Link to invocation

brb-nv added 4 commits March 6, 2026 01:18
Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
This reverts commit c2bec85.

Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
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brb-nv force-pushed the user/brb/helix-for-dsv3.2 branch from d7b1fb0 to 1c114fd Compare March 6, 2026 01:19
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brb-nv commented Mar 6, 2026

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/bot run --disable-fail-fast

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PR_Github #37934 [ run ] triggered by Bot. Commit: 1c114fd Link to invocation

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PR_Github #37934 [ run ] completed with state SUCCESS. Commit: 1c114fd
/LLM/main/L0_MergeRequest_PR pipeline #29378 completed with status: 'SUCCESS'
Pipeline has performance regression cases. Check the performance regression report for details.

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brb-nv merged commit ac8bc6e into NVIDIA:main Mar 6, 2026
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dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Mar 9, 2026
Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
tianyuz-nv pushed a commit to wanqian-nv/TensorRT-LLM that referenced this pull request Mar 19, 2026
Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
limin2021 pushed a commit to limin2021/TensorRT-LLM that referenced this pull request Mar 19, 2026
Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
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8 participants