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[https://nvbugs/6185146][fix] Use mat_a.new_empty([m, n_out//2]) / input_scale.new_empty([sf_size]) in the - #14710

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NVIDIA:mainfrom
tensorrt-cicd:repair-bot-bug6185146
Jun 24, 2026
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[https://nvbugs/6185146][fix] Use mat_a.new_empty([m, n_out//2]) / input_scale.new_empty([sf_size]) in the#14710
peaceh-nv merged 2 commits into
NVIDIA:mainfrom
tensorrt-cicd:repair-bot-bug6185146

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@tensorrt-cicd tensorrt-cicd commented May 28, 2026

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Summary

  • Root cause: The fused fp4out shared-expert custom op's fake fn used positional torch.empty(m,...) (losing SymInt linkage in the FX graph) and the call site used m >= 128 (creating a SymBool guard), so piecewise_optimizer could not find a placeholder SymInt equal to compile_time_num_tokens for the m>=128 compile branch.
  • Fix: Use mat_a.new_empty([m, n_out//2]) / input_scale.new_empty([sf_size]) in the fp4out fake fn, and skip m >= _FP4OUT_MIN_M under torch.compiler.is_compiling() (kernel pads m to CTA tile internally, so fp4_out=True is safe). Remove the now-passing waiver.
  • Automated fix generated by repair-bot

Test plan

  • Verify fix on the same GPU type as the original failure
  • Check for regressions in related tests

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Summary by CodeRabbit

Release Notes

  • Refactor

    • Optimized memory allocation in CUDA operations and improved compiler integration logic.
  • Tests

    • Re-enabled validation of a previously skipped integration test.

Review Change Stack

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No actionable comments were generated in the recent review. 🎉

ℹ️ Recent review info
⚙️ Run configuration

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Review profile: CHILL

Plan: Enterprise

Run ID: a4a5ae59-e820-4d0c-b78e-a1d0fda4e0a0

📥 Commits

Reviewing files that changed from the base of the PR and between f6ba936 and 193e07d.

📒 Files selected for processing (3)
  • tensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.py
  • tensorrt_llm/_torch/modules/gated_mlp.py
  • tests/integration/test_lists/waives.txt
💤 Files with no reviewable changes (1)
  • tests/integration/test_lists/waives.txt

📝 Walkthrough

Walkthrough

This PR optimizes the FP4-output CuTe DSL kernel path for torch.compile by updating memory allocation in the fake custom op and adjusting kernel selection logic in GatedMLP to avoid SymBool guards, enabling correct CUDA graph piecewise capture. A passing test waiver is removed.

Changes

FP4 Output Kernel Path Optimization

Layer / File(s) Summary
FP4 Output Memory Allocation
tensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.py
FP4 output and scale tensors now use new_empty on input tensors rather than explicit torch.empty, and FP4 output shape is derived from list(mat_a.shape) with the last dimension set to n_out // 2, preserving SymInt linkage for the token dimension.
FP4 Output Kernel Selection in GatedMLP
tensorrt_llm/_torch/modules/gated_mlp.py
Fused GEMM+SwiGLU forward now forces FP4-output kernel during torch.compiler.is_compiling() to avoid SymInt comparison guards; otherwise applies _FP4OUT_MIN_M threshold on computed token dimension.
Test Waiver Removal
tests/integration/test_lists/waives.txt
Removes the TestDeepSeekV3Lite::test_cute_dsl_nvfp4_4gpus waiver entry, confirming the FP4 output kernel and CUDA graph capture fix.

Estimated code review effort

🎯 2 (Simple) | ⏱️ ~12 minutes

Possibly related PRs

  • NVIDIA/TensorRT-LLM#14523: Both PRs modify tests/integration/test_lists/waives.txt by updating different waiver entries for TestDeepSeekV3Lite CUTLASS/nvfp4 integration tests.

Suggested reviewers

  • liji-nv
  • symphonylyh
  • jdebache
  • hyukn
🚥 Pre-merge checks | ✅ 3 | ❌ 2

❌ Failed checks (2 warnings)

Check name Status Explanation Resolution
Title check ⚠️ Warning The title is incomplete and appears to be cut off mid-sentence, making it unclear what the complete change entails. Complete the title by adding the missing portion after 'in the' to clearly summarize the change, such as 'fake implementation' or the specific function name.
Docstring Coverage ⚠️ Warning Docstring coverage is 0.00% which is insufficient. The required threshold is 80.00%. Write docstrings for the functions missing them to satisfy the coverage threshold.
✅ Passed checks (3 passed)
Check name Status Explanation
Description check ✅ Passed The PR description provides a clear summary of root cause and fix, identifies the specific files changed, and includes test verification and bug tracking information.
Linked Issues check ✅ Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check ✅ Passed Check skipped because no linked issues were found for this pull request.

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tensorrt-cicd force-pushed the repair-bot-bug6185146 branch 3 times, most recently from 3cc1518 to 70e3072 Compare June 5, 2026 23:05
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peaceh-nv enabled auto-merge (squash) June 9, 2026 06:38
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Fix the DCO issue with sign-off

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peaceh-nv force-pushed the repair-bot-bug6185146 branch from 70e3072 to 2e39ffe Compare June 9, 2026 07:15
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…d fp4out shared-expert path

The CuTe-DSL fused GEMM+SwiGLU+quant shared-expert path (PR NVIDIA#11897) broke
TestDeepSeekV3Lite::test_cute_dsl_nvfp4_4gpus with torch_compile=True +
piecewise CUDA graph. piecewise_optimizer raised
"Cannot identify dynamic shape" because, on the m >= 128 branch:

1. The fake function for cute_dsl_nvfp4_dense_gemm_swiglu_fp4out_blackwell
   used positional torch.empty(m, n_out // 2, ...), which did not propagate
   the input's token-dim SymInt into the FX graph the same way that
   mat_a.new_empty([...]) does (matching the BF16 fake and nvfp4_gemm fake).

2. fp4_out=m >= GatedMLP._FP4OUT_MIN_M produced a SymBool that, when
   consumed by `if fp4_out:` in _fused_gate_up_swiglu, forced a guard on
   the dynamic token dim during torch.compile + piecewise capture.

Fix: switch the fake function to mat_a.new_empty / input_scale.new_empty,
and skip the data-dependent m >= MIN_M check while compiling (the kernel
already pads m up to the CTA tile height internally, so fp4_out is safe at
any m). Also remove the corresponding waives.txt entry.

Signed-off-by: tensorrt-cicd <90828364+tensorrt-cicd@users.noreply.github.com>
Signed-off-by: peaceh <103117813+peaceh-nv@users.noreply.github.com>
Signed-off-by: peaceh <103117813+peaceh-nv@users.noreply.github.com>
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peaceh-nv force-pushed the repair-bot-bug6185146 branch from b418db4 to 9c32fb4 Compare June 23, 2026 05:49
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peaceh-nv merged commit dd13680 into NVIDIA:main Jun 24, 2026
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xinhe-nv pushed a commit to tensorrt-cicd/TensorRT-LLM that referenced this pull request Jun 24, 2026
…`input_scale.new_empty([sf_size])` in the (NVIDIA#14710)

Signed-off-by: tensorrt-cicd <90828364+tensorrt-cicd@users.noreply.github.com>
Signed-off-by: GitLab CI Bot <gitlab-ci@nvidia.com>
BrianLi23 pushed a commit to BrianLi23/TensorRT-LLM that referenced this pull request Jul 9, 2026
…`input_scale.new_empty([sf_size])` in the (NVIDIA#14710)

Signed-off-by: tensorrt-cicd <90828364+tensorrt-cicd@users.noreply.github.com>
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