[https://nvbugs/6473374][fix] Hoist the isinstance check out of the helper at the single call site in… - #16637
[https://nvbugs/6473374][fix] Hoist the isinstance check out of the helper at the single call site in…#16637trtllm-agent wants to merge 2 commits into
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WalkthroughChangesMLA slicing behavior
Estimated code review effort: 2 (Simple) | ~10 minutes Possibly related PRs
Suggested labels: Suggested reviewers: 🚥 Pre-merge checks | ✅ 5✅ Passed checks (5 passed)
✨ Finishing Touches🧪 Generate unit tests (beta)
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/bot run --only-qa-verify test accuracy/test_llm_api_pytorch.py::TestDeepSeekV3Lite::test_nvfp4[moe_backend=CUTLASS-mtp_nextn=2-fp8kv=False-attention_dp=False-cuda_graph=False-overlap_scheduler=False-torch_compile=True] |
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PR_Github #60527 [ run ] triggered by Bot. Commit: |
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PR_Github #60527 [ run ] completed with state |
BowenFu
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LGTM. The hoisted plain-tensor path (mla.py:1422) is byte-identical to the helper's non-Fp4 branch (mla.py:95); FP4 callers still route through the helper, and the change only moves the FX-graph call boundary. Waiver change is a removal. Codex-confirmed no other executable callers of the helper.
| # boundary otherwise shifts multi-stream sync-event insertion around the | ||
| # piecewise CUDA graph regions, producing an async CUDA IMA at sampler | ||
| # event synchronize on SM120 + torch_compile + MTP=2 (nvbugs/6473374). | ||
| if isinstance(hidden_states, Fp4QuantizedTensor): |
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The explanation does not make sense. The _slice_hidden_states_to_num_tokens already shortcut the non-FP4 tensor path. And the forward_impl is inside the MLA custom op and not visible for fx graph.
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ZhanruiSunCh
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LGTM for infra part.
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…forward_impl slice helper On SM120 (RTX PRO 6000 Blackwell Server Edition), the fused NVFP4 kernel is disabled by RMSNorm's SM guard and no Fp4QuantizedTensor is ever produced. But MLA.forward_impl still calls _slice_hidden_states_to_num_tokens, whose outlined function-call boundary shifts multi-stream sync-event insertion around piecewise CUDA graph regions under torch.compile (enable_piecewise_cuda_graph=True, max_num_streams=3), producing an async CUDA IMA at spec sampler event synchronize on the mtp_nextn=2 + torch_compile=True config. Hoist the isinstance check out of the helper so the plain-tensor path takes an inline slice (matching the pre-501777ac89 FX-node shape) while the Fp4QuantizedTensor path still goes through the swizzled-SF-aware helper. No behavior change for the fused NVFP4 boundary fold on SM 10.x. Signed-off-by: trtllm-agent <296075020+trtllm-agent@users.noreply.github.com>
Signed-off-by: handongl <handongl@nvidia.com>
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Note GitHub couldn't provide a complete incremental comparison for this pull request, so CodeRabbit is performing a full review instead. This review may take a little longer. |
Summary
hidden_states[:num_tokens, ...](restoring the pre-501777ac89 FX-node shape) while Fp4QuantizedTensor callers still go through the swizzled-SF-aware helper; also remove the now-fixed waiver.Test plan
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Dev Engineer Review
MLA.forward_implnow uses an inline slice for plain tensors.Fp4QuantizedTensorinputs still use_slice_hidden_states_to_num_tokens.tests/integration/test_lists/waives.txtremoves eight RTX PRO 6000 Blackwell waiver entries.QA Engineer Review
test-db/orqa/files were modified.mtp_nextn=2cases, and two DeepSeekV3Lite NVFP4 cases.