Develop

.gitmodules

@@ -11,7 +11,13 @@
 	path = src/replace
 	url = https://github.com/The-OpenROAD-Project/RePlAce.git
 	branch = openroad
+[submodule "src/ioPlacer"]
+	path = src/ioPlacer
+	url = https://github.com/The-OpenROAD-Project/ioPlacer.git
 [submodule "src/opendp"]
 	path = src/opendp
 	url = https://github.com/The-OpenROAD-Project/OpenDP.git
 	branch = openroad
+[submodule "src/FastRoute4-lefdef"]
+	path = src/FastRoute4-lefdef
+	url = https://github.com/The-OpenROAD-Project/FastRoute4-lefdef.git

README.md

@@ -49,6 +49,8 @@ There are a set of regression tests in `/test`.
 
 ```
 test/regression fast
+src/resizer/test/regression fast
+
 ```
 
 #### Run
@@ -150,7 +152,7 @@ Place pins around core boundary.
 Gate resizer commands are shown below.
 
 ```
-set_wire_rc [-resistance res ] [-capacitance cap] [-corner corner_name]
+set_wire_rc [-layer layer_name] [-resistance res ] [-capacitance cap] [-corner corner_name]
 resize [-buffer_inputs]
        [-buffer_outputs]
        [-resize]
@@ -163,17 +165,21 @@ resize [-buffer_inputs]
 report_design_area
 ```
 
-The `set_wire_rc` command sets the resistance (liberty
-resistance_unit/distance_unit) and capacitance (liberty
-capacitance_unit/distance_unit) of routing wires. It adds RC
-parasitics based on placed component pin locations. If there are no
-component locations no parasitics are added. The resistance and
-capacitance are per distance unit of a routing wire. Use the
-`set_units` command to check units or `set_cmd_units` to change
-units. They should represent "average" routing layer resistance and
-capacitance. If the set_wire_rc command is not called before resizing,
-the default_wireload model specified in the first liberty file or with
-the SDC set_wire_load command is used to make parasitics.
+The `set_wire_rc` command sets the resistance and capacitance used to
+estimate delay of routing wires.  Use `-layer` or `-resistance` and
+`-capacitance`.  If `-layer` is used, the LEF technology resistance
+and area/edge capacitance values for the layer are used.  The units
+for `-resistance` and `-capacitance` are from the first liberty file
+read, resistance_unit/distance_unit and liberty
+capacitance_unit/distance_unit. RC parasitics are added based on
+placed component pin locations. If there are no component locations no
+parasitics are added. The resistance and capacitance are per distance
+unit of a routing wire. Use the `set_units` command to check units or
+`set_cmd_units` to change units. They should represent "average"
+routing layer resistance and capacitance. If the set_wire_rc command
+is not called before resizing, the default_wireload model specified in
+the first liberty file or with the SDC set_wire_load command is used
+to make parasitics.
 
 The `resize` command buffers inputs and outputs, resizes gates, and
 then uses buffer insertion to repair maximum capacitance and slew

include/openroad/OpenRoad.hh

@@ -28,6 +28,14 @@ class dbNetwork;
 class Resizer;
 }
 
+namespace ioPlacer {
+class IOPlacementKernel;
+}
+
+namespace FastRoute {
+class FastRouteKernel;
+}
+
 namespace opendp {
 class opendp_external;
 }
@@ -78,7 +86,9 @@ private:
   dbVerilogNetwork *verilog_network_;
   sta::dbSta *sta_;
   sta::Resizer *resizer_;
+  ioPlacer::IOPlacementKernel *ioPlacer_;
   opendp::opendp_external *opendp_;
+  FastRoute::FastRouteKernel *fastRoute_;
 
   // Singleton used by tcl command interpreter.
   static OpenRoad *openroad_;

src/CMakeLists.txt

@@ -21,6 +21,10 @@ set(OPENDB_WRAP ${CMAKE_CURRENT_BINARY_DIR}/OpenDB_wrap.cc)
 set(RESIZER_HOME ${PROJECT_SOURCE_DIR}/src/resizer)
 set(OPENDP_HOME ${PROJECT_SOURCE_DIR}/src/opendp)
 
+set(IOPLACER_HOME ${PROJECT_SOURCE_DIR}/src/ioPlacer)
+
+set(FASTROUTE_HOME ${PROJECT_SOURCE_DIR}/src/FastRoute4-lefdef)
+
 set(OPENROAD_WRAP ${CMAKE_CURRENT_BINARY_DIR}/OpenRoad_wrap.cc)
 set(OPENROAD_TCL_INIT ${CMAKE_CURRENT_BINARY_DIR}/OpenRoadTclInitVar.cc)
 
@@ -68,17 +72,6 @@ add_custom_command(OUTPUT ${OPENROAD_WRAP}
   DEPENDS OpenRoad.i InitFloorplan.i
   )
 
-################################################################
-
-add_subdirectory(OpenDB)
-add_subdirectory(OpenSTA)
-add_subdirectory(dbSta)
-add_subdirectory(resizer)
-add_subdirectory(flute3)
-add_subdirectory(replace)
-add_subdirectory(opendp)
-
-################################################################
 
 ################################################################
 #
@@ -155,6 +148,23 @@ if (NOT TCL_HEADER)
 endif()
 message(STATUS "TCL header: ${TCL_HEADER}")
 get_filename_component(TCL_HEADER_DIR "${TCL_HEADER}" PATH)
+include_directories(SYSTEM ${TCL_HEADER_DIR})
+
+################################################################
+
+# Disable OpenDB stand-alone executable builds.
+# Simplistic findTCL fails on OSX.
+set(BUILD_PYTHON false)
+set(BUILD_TCL false)
+add_subdirectory(OpenDB)
+add_subdirectory(OpenSTA)
+add_subdirectory(dbSta)
+add_subdirectory(resizer)
+add_subdirectory(flute3)
+add_subdirectory(replace)
+add_subdirectory(opendp)
+add_subdirectory(ioPlacer)
+add_subdirectory(FastRoute4-lefdef)
 
 ################################################################
 
@@ -168,17 +178,20 @@ target_include_directories(openroad
   ${OPENROAD_HOME}/src
   ${OPENDB_HOME}/include
   ${OPENDP_HOME}/include
+  ${FASTROUTE_HOME}/include
   flute3
   )
 
 target_link_libraries(openroad
   replace
   opendp
   resizer
+  ioPlacer
   flute
   dbSta
   OpenSTA
   opendb
+  FR4lefdef
   zutil 
   zlib 
   tm
@@ -194,6 +207,10 @@ if (ZLIB_FOUND)
   target_link_libraries(openroad ${ZLIB_LIBRARIES})
 endif()
 
+if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
+  target_link_libraries(openroad -pthread)
+endif()
+
 target_compile_options(openroad PUBLIC ${COMPILE_OPTIONS})
 
 ################################################################
@@ -203,8 +220,7 @@ target_compile_options(openroad PUBLIC ${COMPILE_OPTIONS})
 # executable
 install(TARGETS openroad DESTINATION bin)
 # etc magic flute files
-INSTALL( FILES ../etc/POST9.dat DESTINATION etc)
-INSTALL( FILES ../etc/POWV9.dat DESTINATION etc)
+install(FILES ../etc/POST9.dat ../etc/POWV9.dat DESTINATION etc)
 
 ################################################################
 
@@ -219,3 +235,4 @@ add_custom_target(openroad_tags etags -o TAGS
   WORKING_DIRECTORY ${OPENROAD_HOME}/src
   DEPENDS ${OPENROAD_SOURCE} ${OPENROAD_HEADERS} ${OPENROAD_TCL_FILES}
   )
+

src/OpenRoad.cc

@@ -28,10 +28,15 @@
 #include "openroad/InitOpenRoad.hh"
 #include "InitFlute.hh"
 
+
+#include "ioPlacer/src/MakeIoplacer.h"
+
 #include "resizer/MakeResizer.hh"
 #include "opendp/MakeOpendp.h"
 #include "replace/src/MakeReplace.h"
 
+#include "FastRoute4-lefdef/src/MakeFastRoute.h"
+
 namespace sta {
 extern const char *openroad_tcl_inits[];
 }
@@ -41,6 +46,8 @@ extern "C" {
 extern int Openroad_Init(Tcl_Interp *interp);
 extern int Opendbtcl_Init(Tcl_Interp *interp);
 extern int Replace_Init(Tcl_Interp *interp);
+extern int Ioplacer_Init(Tcl_Interp *interp);
+extern int Fastroute_Init(Tcl_Interp *interp);
 }
 
 namespace ord {
@@ -93,8 +100,10 @@ OpenRoad::init(Tcl_Interp *tcl_interp,
   db_ = dbDatabase::create();
   sta_ = makeDbSta();
   verilog_network_ = makeDbVerilogNetwork();
+  ioPlacer_ = (ioPlacer::IOPlacementKernel*) makeIoplacer();
   resizer_ = makeResizer();
   opendp_ = makeOpendp();
+  fastRoute_ = (FastRoute::FastRouteKernel*) makeFastRoute();
 
   // Init components.
   Openroad_Init(tcl_interp);
@@ -105,10 +114,12 @@ OpenRoad::init(Tcl_Interp *tcl_interp,
   initDbSta(this);
   initResizer(this);
   initDbVerilogNetwork(this);
+  initIoplacer(this);
   initFlute(prog_arg);
   initReplace(this);
   initOpendp(this);
-
+  initFastRoute(this);
+
   // Import exported commands to global namespace.
   Tcl_Eval(tcl_interp, "sta::define_sta_cmds");
   Tcl_Eval(tcl_interp, "namespace import sta::*");

src/resizer/src/Resizer.i

@@ -130,7 +130,7 @@ wire_resistance()
 
 // farads/meter
 double
-wire_capacitance()
+wire_capacitanceb()
 {
   Resizer *resizer = getResizer();
   return resizer->wireCapacitance();

src/resizer/src/Resizer.tcl

@@ -19,28 +19,55 @@ namespace eval sta {
 # Defined by SWIG interface Resizer.i.
 define_cmd_args "set_dont_use" {cell dont_use}
 
-define_cmd_args "set_wire_rc" {[-resistance res ][-capacitance cap]\
+define_cmd_args "set_wire_rc" {[-layer layer_name]\
+				 [-resistance res ][-capacitance cap]\
 				 [-corner corner_name]}
 
 proc set_wire_rc { args } {
    parse_key_args "set_wire_rc" args \
-    keys {-resistance -capacitance -corner} flags {}
+    keys {-layer -resistance -capacitance -corner} flags {}
 
   set wire_res 0.0
-  if [info exists keys(-resistance)] {
-    set res $keys(-resistance)
-    check_positive_float "-resistance" $res
-  }
   set wire_cap 0.0
-  if [info exists keys(-capacitance)] {
-    set cap $keys(-capacitance)
-    check_positive_float "-capacitance" $cap
+
+  if { [info exists keys(-layer)] } {
+    if { [info exists keys(-resistance)] \
+	   || [info exists keys(-capacitance)] } {
+      sta_error "Use -layer or -resistance/-capacitance but not both."
+    }
+    set layer_name $keys(-layer)
+    set layer [[[ord::get_db] getTech] findLayer $layer_name]
+    if { $layer == "NULL" } {
+      sta_error "layer $layer_name not found."
+    }
+    set layer_width [ord::dbu_to_microns [$layer getWidth]]
+    set res_ohm_per_micron [expr [$layer getResistance] / $layer_width]
+    set cap_pf_per_micron [expr [ord::dbu_to_microns 1] * $layer_width \
+			     * [$layer getCapacitance] \
+			     + [$layer getEdgeCapacitance] * 2]
+    # ohms/sq
+    set wire_res [expr $res_ohm_per_micron * 1e+6]
+    # F/m^2
+    set wire_cap [expr $cap_pf_per_micron * 1e-12 * 1e+6]
+    puts "$wire_res $wire_cap"
+  } else {
+    if { [info exists keys(-resistance)] } {
+      set res $keys(-resistance)
+      check_positive_float "-resistance" $res
+      set wire_res [expr [resistance_ui_sta $res] / [distance_ui_sta 1.0]]
+    }
+
+    if { [info exists keys(-capacitance)] } {
+      set cap $keys(-capacitance)
+      check_positive_float "-capacitance" $cap
+      set wire_cap [expr [capacitance_ui_sta $cap] / [distance_ui_sta 1.0]]
+    }
   }
+
   set corner [parse_corner keys]
   check_argc_eq0 "set_wire_rc" $args
-  set r [expr [resistance_ui_sta $res] / [distance_ui_sta 1.0]]
-  set c [expr [capacitance_ui_sta $cap] / [distance_ui_sta 1.0]]
-  set_wire_rc_cmd $r $c $corner
+
+  set_wire_rc_cmd $wire_res $wire_cap $corner
 }
 
 define_cmd_args "resize" {[-buffer_inputs]\

src/resizer/test/liberty1.lef

@@ -15,6 +15,9 @@ LAYER M1
   WIDTH 0.1 ;
   OFFSET 0.1 ;
   AREA 0.042 ;
+  RESISTANCE RPERSQ 0.38 ;
+  CAPACITANCE CPERSQDIST 7.7161e-05 ;
+  EDGECAPACITANCE 2.7365e-05 ;
 END M1
 
 LAYER M2
@@ -24,6 +27,9 @@ LAYER M2
   WIDTH 0.1 ;
   OFFSET 0.1 ;
   AREA 0.052 ;
+  RESISTANCE RPERSQ 0.25 ;
+  CAPACITANCE CPERSQDIST 4.0896e-05 ;
+  EDGECAPACITANCE 2.5157e-05 ;
 END M2
 
 SITE site1

src/resizer/test/make_parasitics1.ok

@@ -10,35 +10,6 @@ Notice 0:     Created 5 components and 24 component-terminals.
 Notice 0:     Created 2 special nets and 10 connections.
 Notice 0:     Created 7 nets and 14 connections.
 Notice 0: Finished DEF file: reg3.def
-Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
-Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
-Path Group: clk
-Path Type: max
-
-  Delay    Time   Description
----------------------------------------------------------
-   0.00    0.00   clock clk (rise edge)
-   0.00    0.00   clock network delay (ideal)
-   0.00    0.00 ^ r2/CP (snl_ffqx1)
-   0.23    0.23 v r2/Q (snl_ffqx1)
-   0.14    0.37 v u1/Z (snl_bufx1)
-   0.13    0.50 v u2/Z (snl_and02x1)
-   0.00    0.50 v r3/D (snl_ffqx1)
-           0.50   data arrival time
-
-  10.00   10.00   clock clk (rise edge)
-   0.00   10.00   clock network delay (ideal)
-   0.00   10.00   clock reconvergence pessimism
-          10.00 ^ r3/CP (snl_ffqx1)
-  -0.10    9.90   library setup time
-           9.90   data required time
----------------------------------------------------------
-           9.90   data required time
-          -0.50   data arrival time
----------------------------------------------------------
-           9.40   slack (MET)
-
-
 Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
 Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
 Path Group: clk