Documentation: Tweak text about Zero Latency Interrupts#15122
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xiaoxiang781216 merged 1 commit intoDec 10, 2024
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This is a follow-up to 366c8a5 (PR-15102). * Documentation/guides/zerolatencyinterrupts.rst (Title): Make title case consistent. (Getting Back into the Game, Maskable Nested Interrupts): Clarify discussion about priorities. (Cortex-M3/4 Implementation): The first half of a sentence was deleted in 366c8a5 because the Kconfig that was described there no longer exists: CONFIG_ARMV7M_USEBASEPRI. Write a new beginning for this sentence that matches current implementation. (Disabling the High Priority Interrupt): Change "cannot" to "must not be allowed to" to improve clarity. (Configuring High Priority Interrupts): Change "to NVIC" to "in NVIC" to improve clarity.
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[Experimental Bot, please feedback here] Yes, this PR appears to meet the NuttX requirements. The summary clearly explains the purpose, the impact section is comprehensive, and while there's no executable test code, the nature of the change (documentation update) justifies the "proofreading" approach to testing. The cross-referencing to prior PRs is also helpful. |
xiaoxiang781216
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Dec 10, 2024
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This is a follow-up to 366c8a5 (PR #15102).
Note: Please adhere to Contributing Guidelines.
Summary
This is a follow-up to PR #15102, which is itself a follow-up to several PRs: PR #15073, PR #15086. Previously, there were two alternative implementations for enabling and disabling interrupts on ARM Cortex M3/M4 (armv7m, armv8m) architectures: PRIMASK or BASEPRI. BASEPRI is better than PRIMASK in that it is a superset of PRIMASK functionality. Previously there was a Kconfig option, CONFIG_ARMV7M_USEBASEPRI, to choose which implementation was used, and conditional logic in the code. This Kconfig and alternative PRIMASK implementation were removed and BASEPRI is always used now.
This follow-up tweaks some of the Documentation about Zero Latency Interrupts to improve clarity.
Impact
Improved documentation. No functional changes in the OS.
Testing
Proofreading. :-)