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[COSIM][baseline] understand the mismatched latency between phism and csim

case study

Status: Open.

#26 In kumasento/polsca;

· kumasento opened on Sep 18, 2021

[SYNTH][deriche] cannot synth exp2f

bugSomething isn't workingSomething isn't working

wontfixThis will not be worked onThis will not be worked on

Status: Open.

#24 In kumasento/polsca;

· kumasento opened on Sep 17, 2021

[COSIM][symm] csim interface purged some ports

bugSomething isn't workingSomething isn't working

Status: Open.

#23 In kumasento/polsca;

· kumasento opened on Sep 17, 2021

[COSIM][correlation] Weird memory port generated from C sim

bugSomething isn't workingSomething isn't working

Status: Open.

#22 In kumasento/polsca;

· kumasento opened on Sep 17, 2021

[POLYBENCH][CASE STUDY] trmm: use outer indvars as inner bounds

case study

Status: Open.

#21 In kumasento/polsca;

· kumasento opened on Sep 17, 2021

[COSIM][2mm][SMALL] mismatched ports

bugSomething isn't workingSomething isn't working

Status: Open.

#19 In kumasento/polsca;

· kumasento opened on Sep 16, 2021