[COSIM][symm] csim interface purged some ports

[kumasento]

Pb-flow logs:

[2021-09-17 15:13:16,491][pb-flow][DEBUG] Parameters parsed from /mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/tb/solution1/syn/verilog/kernel_symm.v:
ap_clk
ap_rst
ap_start
ap_done
ap_idle
ap_ready
m
n
alpha
beta
C_address0
C_ce0
C_we0
C_d0
C_q0
C_address1
C_ce1
C_we1
C_d1
C_q1
A_address0
A_ce0
A_q0
B_address0
B_ce0
B_q0
[2021-09-17 15:13:16,493][pb-flow][DEBUG] Parameters parsed from /mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/tb/solution1/sim/verilog/kernel_symm.autotb.v:
ap_clk
ap_rst
ap_start
ap_done
ap_idle
ap_ready
m
n
alpha
beta
C_address0
C_ce0
C_we0
C_d0
C_q0
A_address0
A_ce0
A_q0
B_address0
B_ce0
B_q0
[2021-09-17 15:13:16,494][pb-flow][DEBUG] Parsed memory interfaces from /mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/tb/solution1/syn/verilog/kernel_symm.v:
ApMemoryInterface(name='C', ports=['address0', 'ce0', 'we0', 'd0', 'q0', 'address1', 'ce1', 'we1', 'd1', 'q1'])
ApMemoryInterface(name='A', ports=['address0', 'ce0', 'q0'])
ApMemoryInterface(name='B', ports=['address0', 'ce0', 'q0'])
[2021-09-17 15:13:16,494][pb-flow][DEBUG] Parsed memory interfaces from /mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/tb/solution1/sim/verilog/kernel_symm.autotb.v:
ApMemoryInterface(name='C', ports=['address0', 'ce0', 'we0', 'd0', 'q0'])
ApMemoryInterface(name='A', ports=['address0', 'ce0', 'q0'])
ApMemoryInterface(name='B', ports=['address0', 'ce0', 'q0'])
[2021-09-17 15:13:16,494][pb-flow][DEBUG] Cosim interface is not matched between /mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/tb/solution1/syn/verilog/kernel_symm.v and /mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/tb/solution1/sim/verilog/kernel_symm.autotb.v. Trying to fix.
[2021-09-17 15:13:16,494][pb-flow][DEBUG] Cosim fix strategy:
	Phism directives: []
	Tbgen directives: ['set_directive_interface -mode ap_memory -storage_type ram_2p kernel_symm C']
[2021-09-17 15:13:16,496][pb-flow][DEBUG] Re-run csim on the updated tbgen.tcl file.
[2021-09-17 15:13:16,497][pb-flow][WARNING] CSim is set to be skipped.
[2021-09-17 15:13:16,497][pb-flow][DEBUG] Toggled -setup to cosim_design.
[2021-09-17 15:13:16,715][pb-flow][DEBUG] Removed old /mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/tb
[2021-09-17 15:13:16,720][pb-flow][DEBUG] vitis_hls \
	/mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/tbgen.tcl
[2021-09-17 15:14:42,794][pb-flow][DEBUG] csim_dir=/mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/tb.csim exists, deleting it ...
[2021-09-17 15:14:44,689][pb-flow][DEBUG] Design files found: 
/mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/proj/solution1/syn/verilog/kernel_symm_ap_dmul_4_max_dsp_64_ip.tcl
/mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/proj/solution1/syn/verilog/DAcc_ip.tcl
/mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/proj/solution1/syn/verilog/AESL_FPSim_pkg.v
/mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/proj/solution1/syn/verilog/kernel_symm.v
/mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/proj/solution1/syn/verilog/kernel_symm_dadd_64ns_64ns_64_7_full_dsp_1.v
/mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/proj/solution1/syn/verilog/kernel_symm_ap_dadd_5_full_dsp_64_ip.tcl
/mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/proj/solution1/syn/verilog/kernel_symm_dacc_64ns_64ns_1ns_64_4_med_dsp_1.v
/mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/proj/solution1/syn/verilog/kernel_symm_mul_5ns_6ns_10_1_1.v
/mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/proj/solution1/syn/verilog/kernel_symm_dmul_64ns_64ns_64_6_max_dsp_1.v
[2021-09-17 15:14:44,693][pb-flow][DEBUG] Parameters parsed from /mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/tb/solution1/syn/verilog/kernel_symm.v:
ap_clk
ap_rst
ap_start
ap_done
ap_idle
ap_ready
m
n
alpha
beta
C_address0
C_ce0
C_we0
C_d0
C_q0
C_address1
C_ce1
C_we1
C_d1
C_q1
A_address0
A_ce0
A_q0
B_address0
B_ce0
B_q0
[2021-09-17 15:14:44,695][pb-flow][DEBUG] Parameters parsed from /mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/tb/solution1/sim/verilog/kernel_symm.autotb.v:
ap_clk
ap_rst
ap_start
ap_done
ap_idle
ap_ready
m
n
alpha
beta
C_address0
C_ce0
C_q0
C_address1
C_ce1
C_we1
C_d1
A_address0
A_ce0
A_q0
B_address0
B_ce0
B_q0
[2021-09-17 15:14:44,695][pb-flow][DEBUG] Parsed memory interfaces from /mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/tb/solution1/syn/verilog/kernel_symm.v:
ApMemoryInterface(name='C', ports=['address0', 'ce0', 'we0', 'd0', 'q0', 'address1', 'ce1', 'we1', 'd1', 'q1'])
ApMemoryInterface(name='A', ports=['address0', 'ce0', 'q0'])
ApMemoryInterface(name='B', ports=['address0', 'ce0', 'q0'])
[2021-09-17 15:14:44,696][pb-flow][DEBUG] Parsed memory interfaces from /mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/tb/solution1/sim/verilog/kernel_symm.autotb.v:
ApMemoryInterface(name='C', ports=['address0', 'ce0', 'q0', 'address1', 'ce1', 'we1', 'd1'])
ApMemoryInterface(name='A', ports=['address0', 'ce0', 'q0'])
ApMemoryInterface(name='B', ports=['address0', 'ce0', 'q0'])
[2021-09-17 15:14:44,696][pb-flow][DEBUG] Cosim interface is not matched between /mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/tb/solution1/syn/verilog/kernel_symm.v and /mnt/ccnas2/bdp/rz3515/projects/phism/tmp/phism/pb-flow.baseline/linear-algebra/blas/symm/tb/solution1/sim/verilog/kernel_symm.autotb.v. Trying to fix.