A fully pipelined 5-stage RV32I processor implemented in SystemVerilog. This design models instruction-level parallelism with forwarding and hazard detection, and passes all RISCOF compliance tests for the RV32I base ISA.

An FPGA implementation of Cummings' Asynchronous FIFO

ARM single cycle processor on nandland.com go-board

Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.

SystemVerilog Solutions to exercise from HDLBits

TPU designed on DE1-SoC FPGA for 4096x4096 sparse MM and convolution for UC Davis Senior Design 2023 with Austin York, Gurkirat Dhillon, and Kent Cassidy.

This repository contains a SystemVerilog implementation of a basic 5-stage pipeline RISC-V processor. The processor includes a register file, ALU, control unit, instruction memory, and data memory. It is designed to run simple assembly programs and includes optimizations for performance such as hazard detection, forwarding, and branch prediction.

learning about FPGA

Implementation of a FIR-filter on a FPGA and its employment in an audio system obtained using a PMOD I2S2.

A simple processor with a grid of cores that can only interact with their immediate neighbors

verilog

A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.

AES Encryption in FPGA.

🔋 SystemVerilog study repository

SPN Cipher in System Verilog using Vivado

Here you'll find the game "Donkey Kong" written 100% in SysVerilog. You'll need an FPGA card, a screen, a keyboard, and audio devices for the full functionality.

A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, for use on the Xilinx Basys 3 board.