registers
Here are 128 public repositories matching this topic...
SystemRDL 2.0 language compiler front-end
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Apr 10, 2026 - C++
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
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Oct 21, 2024 - Verilog
Control and status register code generator toolchain
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Apr 10, 2026 - Python
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
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Mar 28, 2026 - Python
Generate address space documentation HTML from compiled SystemRDL input
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Mar 6, 2026 - JavaScript
C++ templates for type-safe bit manipulation
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Feb 2, 2021 - C
Generate UVM register model from compiled SystemRDL input
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Nov 25, 2025 - Python
Vision Transformers Needs Registers. And Gated MLPs. And +20M params. Tiny modality gap ensues!
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Jun 2, 2025 - Python
A Mewtocol protocol library to interface with Panasonic PLCs over TCP/Serial written in C#
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Feb 17, 2024 - C#
[closed]🔥 virtual machine & assembler-style language 🔥
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May 27, 2021 - C#
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
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Mar 31, 2026 - Verilog
Julia Bit Manipulation Functions
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Nov 29, 2021 - Julia
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