Control and status register code generator toolchain
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Updated
Apr 10, 2026 - Python
Control and status register code generator toolchain
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Generate UVM register model from compiled SystemRDL input
Vision Transformers Needs Registers. And Gated MLPs. And +20M params. Tiny modality gap ensues!
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
Vision Transformers Needs Registers. And Gated MLPs. And +20M params. Tiny modality gap ensues!
Parse register dumps with minimal overhead
A GUI simulator/interpreter for custom assembly language, written in python/tkinter
Smeagle Python - generate facts from ELF with debug
A registration providing the functionalities for a "public documents" storage.
A simulator for executing RISC-V binary instructions with register and memory visualization. Tracks PC, handles all instruction types.
A simulator for executing RISC-V binary instructions with register and memory visualization. Tracks PC, handles all instruction types, and includes bonus operations.
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